search for: rl329871

...of EFLAGS. This preserves the necessary state in a GPR rather than using pushf/popf. [r329657](https://reviews.llvm.org/rL329657). * The RISC-V backend gained support for codegen for the RV32D (double-precision floating point) standard instruction set extension. [r329871](https://reviews.llvm.org/rL329871), [r329874](https://reviews.llvm.org/rL329874), and more. * MIPS GlobalISel now has the minimal support necessary to lower a function that returns the sum of two i32 values. [r329819](https://reviews.llvm.org/rL329819). * The newly added InitLLVM class was added to perform common initialization f...