search for: rl304088

...ts of the register parameter are the first 4, 5 or 6 bits (depending on mode and register size) while in the memory-folded instruction, the relevant bits of the memory operand are the first 16, 32 or 64 bits. A TableGen backend was created for this purpose and committed in https://reviews.llvm.org/rL304088, including a small list of exceptions for cases similar to the bit-test instruction above. After the patch was committed, two more exceptions were found which led to reverting the patch (https://reviews.llvm.org/rL304762). Looking for safe-alternatives that will assure us correctness of each adde...