search for: rl162460

Displaying 2 results from an estimated 2 matches for "rl162460".

2017 Aug 21
3
RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
...or the note - excellent point. Looking at CodeGenDAGPatterns.cpp, it seems in the absence of a pattern hasSideEffects will be 1, while mayLoad and mayStore default to 0. Back in 2012, Jakob Stoklund Olesen added the guessInstructionProperties flag, which causes an error <https://reviews.llvm.org/rL162460> if a property isn't set explicitly and can't be inferred. It doesn't look like any other in-tree targets have ended up enabling this, but it looks like it would be worth enabling for RISCV, particularly if going ahead with splitting instructions and patterns. Best, Alex
2017 Aug 18
5
RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
As many of you know, I have a growing series of patches for a RISC-V backend under/awaiting review <https://reviews.llvm.org/differential/?authors=asb&order=updated>, <http://github.com/lowrisc/riscv-llvm>. I'll be posting a larger status update on that work either later today or tomorrow, this RFC focuses on an issue that came up during review which I think may benefit from