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On Mon, Nov 24, 2014 at 8:33 PM, Andy Ritger <aritger at nvidia.com> wrote: > On Fri, Nov 21, 2014 at 01:39:55AM -0500, Ilia Mirkin wrote: >> On Fri, Nov 21, 2014 at 1:16 AM, Andy Ritger <aritger at nvidia.com> wrote: >> > Hi Ilia, >> > >> > Actually 0x90b8 is different than copy engine. I'...

...d help NVIDIA prioritize our documentation efforts. If you have specific questions for NVIDIA, you can ask here, or direct them to: open-gpu-doc at nvidia.com. I can't promise we'll be able to answer everything, but we'll provide best-effort in areas where we are able. Thanks, - Andy Ritger

On Fri, Nov 21, 2014 at 1:16 AM, Andy Ritger <aritger at nvidia.com> wrote: > Hi Ilia, > > Actually 0x90b8 is different than copy engine. I'm not very familiar > with it, but 0x90b8 is an engine for performing LZO decompression as > part of performing the copy. It has a variety of limitations (e.g., > cannot hand...

Hello, I've recently run into an unknown bit in Tesla shaders, and was hoping you could shed some light on it. I believe they're related to clamping of some sort. Here are 2 examples (from diff shaders): a0000401 cc054780 cvt rpi f32 $r0 f32 $r2 [unknown: 00000000 00010000] a000060d 8c014780 cvt rni s32 $r3 f32 $r3 [unknown: 00000000 00010000] [This is intel-style syntax, cvt =

On 18/09/15 23:30, Andy Ritger wrote: > Thanks, Martin. I'll try to follow up on this next week and get you an answer. What GPUs have you observed this on? > Thanks Andy, As far as I can tell, it is the case for all GPUs using the PWM-based voltage management. To be more specific, we have seen this behaviour on a...

Hi, The VBIOS on GM20x GPUs uses a slightly updated version of the DCB. I've posted an updated DCB spec here: ftp://download.nvidia.com/open-gpu-doc/DCB/2/DCB-4.x-Specification.html You can diff it against the previous version: ftp://download.nvidia.com/open-gpu-doc/DCB/1/DCB-4.0-Specification.html to see what changed (sorry for having to diff html files). The biggest differences are

On Wed, Dec 10, 2014 at 7:36 AM, Ben Skeggs <skeggsb at gmail.com> wrote: > On Wed, Dec 10, 2014 at 4:26 AM, Andy Ritger <aritger at nvidia.com> wrote: >> Hi, > Hey Andy, > >> >> The VBIOS on GM20x GPUs uses a slightly updated version of the DCB. >> I've posted an updated DCB spec here: >> >> ftp://download.nvidia.com/open-gpu-doc/DCB/2/DCB-4.x-Specification.html &g...

On Sat, Dec 13, 2014 at 6:42 PM, Andy Ritger <aritger at nvidia.com> wrote: > On Wed, Dec 10, 2014 at 07:46:16AM +1000, Ben Skeggs wrote: >> On Wed, Dec 10, 2014 at 7:36 AM, Ben Skeggs <skeggsb at gmail.com> wrote: >> > On Wed, Dec 10, 2014 at 4:26 AM, Andy Ritger <aritger at nvidia.com> wrote: >> &gt...

On Tue, Nov 25, 2014 at 10:57:44AM -0500, Ilia Mirkin wrote: > On Mon, Nov 24, 2014 at 8:33 PM, Andy Ritger <aritger at nvidia.com> wrote: > > On Fri, Nov 21, 2014 at 01:39:55AM -0500, Ilia Mirkin wrote: > >> On Fri, Nov 21, 2014 at 1:16 AM, Andy Ritger <aritger at nvidia.com> wrote: > >> > Hi Ilia, > >> > > >> > Actually 0x90b8 is different...

On 23/11/17 10:06, John Hubbard wrote: > On 11/22/2017 05:07 PM, Martin Peres wrote: >> Hey, >> >> Thanks for your answer, Andy! >> >> On 22/11/17 04:06, Ilia Mirkin wrote: >>> On Tue, Nov 21, 2017 at 8:29 PM, Andy Ritger <aritger at nvidia.com> wrote: >>> Martin's question was very long, but it boils down to this: >>> >>> How do we compute the correct values to write into the e114/e118 pwm >>> registers based on the VBIOS contents and current state of the board >>...

Hey, Thanks for your answer, Andy! On 22/11/17 04:06, Ilia Mirkin wrote: > On Tue, Nov 21, 2017 at 8:29 PM, Andy Ritger <aritger at nvidia.com> wrote: >> Hi Martin, > > Martin should have complete answers, > >> >> I was asked to clarify a few things: >> >> (1) Are all the user reports of loud fans on Fermi-era GPUs? > > Yes. Although I believe some GK208 users ar...

On 25/11/14 22:05, Andy Ritger wrote: > On Tue, Nov 25, 2014 at 10:57:44AM -0500, Ilia Mirkin wrote: >> On Mon, Nov 24, 2014 at 8:33 PM, Andy Ritger <aritger at nvidia.com> wrote: >>> On Fri, Nov 21, 2014 at 01:39:55AM -0500, Ilia Mirkin wrote: >>>> On Fri, Nov 21, 2014 at 1:16 AM, Andy Ritger...

Hi, all. Below is a link to a brief document describing some changes in NVIDIA Falcon processors ("fuc", in Nouveau-speak, IIUC) that happened in Maxwell: certain aspects of the chip will only be available to Falcon firmware images signed by NVIDIA. So far, the set of restricted things is pretty small, but I expect this list will slowly grow over future hardware generations.

...0, even in LINKED_TSC mode (i.e. method 0x1234 == 1)? We don't currently make use of that mode in nouveau, but I'm thinking about doing it on Tesla / Fermi so that we can get more than 16 textures per stage on there. Thanks again for the info! -ilia On Wed, Mar 7, 2018 at 3:21 PM, Andy Ritger <aritger at nvidia.com> wrote: > Hi Ilia. > > It looks like there is a hardware bug on Fermi and Kepler where TLD > unconditionally uses the sampler from slot 0. This is supposedly fixed > in Maxwell. What I could find internally suggests the bug wasn't present > on Te...

...0:06, John Hubbard wrote: >>> On 11/22/2017 05:07 PM, Martin Peres wrote: >>>> Hey, >>>> >>>> Thanks for your answer, Andy! >>>> >>>> On 22/11/17 04:06, Ilia Mirkin wrote: >>>>> On Tue, Nov 21, 2017 at 8:29 PM, Andy Ritger <aritger at nvidia.com> wrote: >>>>> Martin's question was very long, but it boils down to this: >>>>> >>>>> How do we compute the correct values to write into the e114/e118 pwm >>>>> registers based on the VBIOS contents and cur...

...2017 05:07 PM, Martin Peres wrote: >>>>>> Hey, >>>>>> >>>>>> Thanks for your answer, Andy! >>>>>> >>>>>> On 22/11/17 04:06, Ilia Mirkin wrote: >>>>>>> On Tue, Nov 21, 2017 at 8:29 PM, Andy Ritger <aritger at nvidia.com> wrote: >>>>>>> Martin's question was very long, but it boils down to this: >>>>>>> >>>>>>> How do we compute the correct values to write into the e114/e118 pwm >>>>>>> registers bas...

Hi Martin, I was asked to clarify a few things: (1) Are all the user reports of loud fans on Fermi-era GPUs? (2) When the VBIOS POSTs the card, it loads initial ucode onto the Falcon processor (PMU), which will do basic fan management on its own. We call this init ucode "IFR" (Init From ROM). nvidia.ko will restore the IFR ucode when unloaded. I assume the loud fan symptom occurs

Hello, We recently reverse engineered PWM-based voltage management but found an odity in the input clock frequency for the PWM controller. It seems like RM is assuming an input clock of 27.648 MHz instead of the actual 27MHz crystal found on the board. I thus have the following questions: - Is it a fixed value hardcoded in RM? (Current way it is done in Nouveau) - Should we use

On 11/22/2017 05:07 PM, Martin Peres wrote: > Hey, > > Thanks for your answer, Andy! > > On 22/11/17 04:06, Ilia Mirkin wrote: >> On Tue, Nov 21, 2017 at 8:29 PM, Andy Ritger <aritger at nvidia.com> wrote: >> Martin's question was very long, but it boils down to this: >> >> How do we compute the correct values to write into the e114/e118 pwm >> registers based on the VBIOS contents and current state of the board >> (like temperatu...

Hey, Op 24-09-13 06:44, Andy Ritger schreef: > Hi Nouveau developers, > > NVIDIA is releasing public documentation on certain aspects of our GPUs, > with the intent to address areas that impact the out-of-the-box usability > of NVIDIA GPUs with Nouveau. We intend to provide more documentation > over time, and guida...