search for: riscvinstrinfo

...patches <https://reviews.llvm.org/differential/?authors=asb&order=updated> is an incredibly valuable way to do so. If you would like to be listed as a reviewer for future patches, just let me know (and feel free to add yourself for existing patches). I'll be doing some refactoring of RISCVInstrInfo.td as discussed here <http://lists.llvm.org/pipermail/llvm-dev/2017-August/116635.html>, but this is a straight-forward non-functional change. Other than that, there are no planned changes to the patches currently up for review. My current plans look like the below, though of course will acc...

...p:97: > /data/project/xiangzhai/llvm/build/lib/Target/RISCV/RISCVGenGlobalISel.inc:100:7: > error: use of > undeclared identifier 'Subtarget' > if (Subtarget->is64Bit()) > ^ > > > Even if no errors after comment `if (Subtarget->is64Bit())` in > RISCVInstrInfo.td, but it is monkey patch, and it can't handle riscv64 > without the if condition check. > > And I noticed there is `if (Subtarget->useMovt(*MF))` in ARMInstrInfo.td too > https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMInstrInfo.td#L694 I haven't looked i...

Hi Im trying to add RISC V Store Instruction for an Experiment on my Target. The thing is, llvm Store Format gets Register and Pointer Type Operand. beside this, RISC-V Store Instruction takes source Register, Base Register and offset immediate type. So this takes 3 leafs. In this case, should I make new SelectionDAG Node in this case? or use BuildMI Instruction to add new Register? P.S.

Alex, ping? There was a thread about moving Risc-V out of experimental but I think it didn't go anywhere? Separately, do the listed patches sound okay for merging? Thanks, Hans On Fri, Jan 25, 2019 at 4:40 PM Bruce Hoult <brucehoult at sifive.com> wrote: > > In https://llvm.org/svn/llvm-project/llvm/branches/release_80 I find > that RISCV is still in