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Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to

...construction, so I use some little weird approach to init target-abi option before construct AsmBackend[1] or reassign target-abi option in getSubtargetImpl and do some hack in backend[2]. 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp) 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) I think [1] and [2] are not good enough, the other ideals like 3. encode target abi info in triple name. ex. riscv64-unknown-elf-lp64d 4. encode target-abi into in target-feature (maybe it's not a good ideal because mips reverted this approach before. http://llvm.org/viewvc/llvm-project?vi...

...proach to init target-abi option before construct >> AsmBackend[1] or reassign target-abi option in getSubtargetImpl and do some >> hack in backend[2]. >> >> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp) >> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >> >> I think [1] and [2] are not good enough, the other ideals like >> >> 3. encode target abi info in triple name. ex. riscv64-unknown-elf-lp64d >> 4. encode target-abi into in target-feature (maybe it's not a good ideal >> because mips reverted this app...

...sign target-abi option in getSubtargetImpl and do some hack in backend[2]. > > 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy <https://reviews.llvm.org/D72245#change-sHyISc6hOqcy> (see llc.cpp) > 2. https://reviews.llvm.org/D72246 <https://reviews.llvm.org/D72246> (see RISCVAsmBackend.h) > > I think [1] and [2] are not good enough, the other ideals like > > 3. encode target abi info in triple name. ex. riscv64-unknown-elf-lp64d > 4. encode target-abi into in target-feature (maybe it's not a good ideal because mips reverted this approach > before. http://...

...abi option in getSubtargetImpl and do some hack in backend[2]. >> >> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy <https://reviews.llvm.org/D72245#change-sHyISc6hOqcy> (see llc.cpp) >> 2. https://reviews.llvm.org/D72246 <https://reviews.llvm.org/D72246> (see RISCVAsmBackend.h) >> >> I think [1] and [2] are not good enough, the other ideals like >> >> 3. encode target abi info in triple name. ex. riscv64-unknown-elf-lp64d >> 4. encode target-abi into in target-feature (maybe it's not a good ideal because mips reverted this approach...

...ckend[1] or reassign target-abi option in >>>>>> getSubtargetImpl and do some hack in backend[2]. >>>>>> >>>>>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp) >>>>>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >>>>>> >>>>>> I think [1] and [2] are not good enough, the other ideals like >>>>>> >>>>>> 3. encode target abi info in triple name. ex. >>>>>> riscv64-unknown-elf-lp64d >>>>>> 4. encode t...

...>> getSubtargetImpl and do some hack in backend[2]. >>>>>>>> >>>>>>>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp >>>>>>>> ) >>>>>>>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >>>>>>>> >>>>>>>> I think [1] and [2] are not good enough, the other ideals like >>>>>>>> >>>>>>>> 3. encode target abi info in triple name. ex. >>>>>>>> riscv64-unknown-elf-lp...

...rd approach to init target-abi option before construct AsmBackend[1] or reassign target-abi option in getSubtargetImpl and do some hack in backend[2]. >>> >>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp) >>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >>> >>> I think [1] and [2] are not good enough, the other ideals like >>> >>> 3. encode target abi info in triple name. ex. riscv64-unknown-elf-lp64d >>> 4. encode target-abi into in target-feature (maybe it's not a good ideal because mips reve...

...t; before construct AsmBackend[1] or reassign target-abi option in >> getSubtargetImpl and do some hack in backend[2]. >> >>> >> >>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp) >> >>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >> >>> >> >>> I think [1] and [2] are not good enough, the other ideals like >> >>> >> >>> 3. encode target abi info in triple name. ex. >> riscv64-unknown-elf-lp64d >> >>> 4. encode target-abi into in target-featur...

...get-abi option in >>>> getSubtargetImpl and do some hack in backend[2]. >>>> >>> >>>> >>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see >>>> llc.cpp) >>>> >>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >>>> >>> >>>> >>> I think [1] and [2] are not good enough, the other ideals like >>>> >>> >>>> >>> 3. encode target abi info in triple name. ex. >>>> riscv64-unknown-elf-lp64d >>>> >&gt...

...gt; before construct AsmBackend[1] or reassign target-abi option in > getSubtargetImpl and do some hack in backend[2]. > > >>> > > >>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see llc.cpp) > > >>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) > > >>> > > >>> I think [1] and [2] are not good enough, the other ideals like > > >>> > > >>> 3. encode target abi info in triple name. ex. > riscv64-unknown-elf-lp64d > > >>> 4. encode target-abi into in target-featu...

...n target-abi option in >>> getSubtargetImpl and do some hack in backend[2]. >>> > >>> >>> > >>> 1. https://reviews.llvm.org/D72245#change-sHyISc6hOqcy (see >>> llc.cpp) >>> > >>> 2. https://reviews.llvm.org/D72246 (see RISCVAsmBackend.h) >>> > >>> >>> > >>> I think [1] and [2] are not good enough, the other ideals like >>> > >>> >>> > >>> 3. encode target abi info in triple name. ex. >>> riscv64-unknown-elf-lp64d >>> > >&g...