search for: risc1

...ly the difference to the remote. I prefer to send the difference of a 500 MB file than sending the whole file over. I use AIX and rsync version rsync version 2.4.5 protocol version 24 Oh and my command is : rsync --stats --progress --delete --partial --timeout=60 --bwlimit=10 -aRtvz patrick@risc1::test /special thank you. -------------- next part -------------- HTML attachment scrubbed and removed

...t tell me anything about the assembly instruction it uses, right? But then also I see as Design "RISC", as I understood it describes the assembly instructions? But why would I tell Clang to target "mips1" when the design of the R3000 is RISC? Why isn't RISCV correct then? Or RISC1 or so... Also how does that influence floating point arithmetic? I often heard that those are separated processors FPUs(?). So could it be, that there is an additional processor besides the processor I know about? Like R3000 + FPU? Wouldn't had Clang or any other compiler to know about such a...

...fffff cx88[0]: cmds: iq rd ptr : 0xffffffff cx88[0]: cmds: cdt current : 0xffffffff cx88[0]: cmds: pci target : 0xffffffff cx88[0]: cmds: line / byte : 0xffffffff cx88[0]: risc0: 0xffffffff [ INVALID sol eol irq2 irq1 23 22 21 20 19 18 cnt1 cnt0 resync 14 13 12 count=4095 ] cx88[0]: risc1: 0xffffffff [ INVALID sol eol irq2 irq1 23 22 21 20 19 18 cnt1 cnt0 resync 14 13 12 count=4095 ] cx88[0]: risc2: 0xffffffff [ INVALID sol eol irq2 irq1 23 22 21 20 19 18 cnt1 cnt0 resync 14 13 12 count=4095 ] cx88[0]: risc3: 0xffffffff [ INVALID sol eol irq2 irq1 23 22 21 20 19 18 cnt1 cnt0...

The term "target" is somewhat overloaded. When llvm-config tells you it was built with the X86 target, that actually includes a variety of closely related architectures, such as x86_64, i386, and so on. Within the x86_64 architecture, there are many individual processor implementations that LLVM understands, such as Skylake, Bulldozer, and many many more. What *clang* means by