search for: richard_barton

...that is currently present > in the AArch64 backend. > > Looking at the failures that are present in the ARM64 backend, it doesn't > look like it would be too much work to fixup the MC layer to get this > testsuite passing. > > [0] http://llvm.org/devmtg/2012-04-12/Slides/Richard_Barton.pdf > > Regards, > Bradley Smith > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...letely for the v6m architecture. Potentially, just making sure that a build with assertions enabled would result in an assertion failure being triggered when a non-v6m instruction gets emitted could be good enough, as a starting point? Thanks, Kristof [1] http://llvm.org/devmtg/2012-04-12/Slides/Richard_Barton.pdf

...h an ARM in-house implementation of the same functionality. The test space for this suite is very large ( O(10 trillion) points ) so we are concentrating on small slices at a time. For further details you can check out the talk I did at EuroLLVM last month: http://llvm.org/devmtg/2012-04-12/Slides/Richard_Barton.pdf Results -------- The below results are: - for Thumb instructions - for Cortex-A8 with VFPv3 and Advanced SIMDv1 extensions - for the encode/decode loop, described on slide 11 of the talk - all silent codegen bugs[1], that is bugs where: - The reference bitpattern is defined and predic...

All, Attached below are the patches that make up the Apple ARM64 compiler backend (in addition to compiler_rt, libc++ and lldb support), and we'd like to start the process of integrating them into mainline LLVM. We and ARM have discussed a general approach to integrating them into mainline and look forward to working through this with the community at large. First a bit of context to help

...h an ARM in-house implementation of the same functionality. The test space for this suite is very large ( O(10 trillion) points ) so we are concentrating on small slices at a time. For further details you can check out the talk I did at EuroLLVM last month: http://llvm.org/devmtg/2012-04-12/Slides/Richard_Barton.pdf Results -------- The below results are: - for ARM instructions (i.e. not Thumb instructions) - for Cortex-A8 with VFPv3 and Advanced SIMDv1 extensions - for the encode/decode loop, described on slide 11 of the talk - for all instruction encodings with condition code AL (all 32-bit pattern...