search for: ric1417175928887

...rm cores ship with direct-mapped caches so I'll admit this is unlikely. The possibility for issues increases if the Exclusives Reservation Granule is larger. For the Cortex-M4, the ERG is the entire address range <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100166_0001_00_en/ric1417175928887.html>. In that case, spills will surely clear the reservation. There also seem to be documented and very strict forward progress constraints for ARMv8-M. See https://static.docs.arm.com/ddi0553/ah/DDI0553A_h_armv8m_arm.pdf p207 """ Forward progress can only be made using LoadExc...

# RFC: Atomic LL/SC loops in LLVM revisited ## Summary This proposal gives a brief overview of the challenges of lowering to LL/SC loops and details the approach I am taking for RISC-V. Beyond getting feedback on that work, my intention is to find consensus on moving other backends towards a similar approach and sharing common code where feasible. Scroll down to 'Questions' for a summary