search for: rgpr

I'm looking at an issue where we want a particular pseudo-instruction to choose from a set of registers that is not included in the existing set of RegisterClass definitions. More concretely, there is a RegisterClass in ARMRegisterInfo.td defined as def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; let AltOrderSelect = [{ return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); }]; } However, I'd like the instruction NOT to use...

Hello, About a month ago, I submitted a set of patches for review on llvm-commit. The most controversial of the patches, http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20150622/d104ea7 1/attachment-0009.obj deals with the fact that before ARMv8, the rGPR RegClass in Thumb encodings didn't include SP; but from ARMv8 onwards, it does include it. RegClass membership is currently implemented as entirely static, driven by read-only TableGen'd tables and switch blocks encoding the various classes, subclasses, and their relationships. The appr...

Jim, Thanks for the hints. Does LLVM allow allocation of the same register across register classes? For example, in the ARM backend, can an instruction write to R0 when it is part of register class tGPR, but then use R0 in the next instruction as a source register from the rGPR class? If LLVM can do this, then this will work. Micah > -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Tuesday, August 16, 2011 9:33 AM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Tying an instruction to a...

Hi, I have a question about the definitions of t2LDRSB and t2LDRSB_PRE in ARMInstrThumb2.td : I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced? defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, rGPR, UnOpFrag<(sextl...

Is there a way in tablegen to specify that a certain instruction can only be allocated with a certain subset of a register class? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110816/329bea6e/attachment.html>

Hi Micah, You can just create a new register class that only contains the registers you want and use that for the instruction. The set theoretic operators for register class definition make this very easy. See the ARM backend definitions of GPRnopc, rGPR, etc.. for examples. -Jim On Aug 16, 2011, at 9:18 AM, Villmow, Micah wrote: > Is there a way in tablegen to specify that a certain instruction can only be allocated with a certain subset of a register class? > > Thanks, > Micah > _______________________________________________...

Hi Junbum, > I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced? They're not allocated during CodeGen because of the Reserved.set(…) calls in ARMBaseRegisterInfo.cpp. That said, this inconsiste...

...ster allocation in writeback version? Thanks, Junbum On May 23, 2013, at 11:51 AM, Tim Northover <tnorthover at apple.com> wrote: > Hi Junbum, > >> I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced? > > They're not allocated during CodeGen because of the Reserved.set(…) calls in ARMBaseRegisterInfo.cpp. > > That s...