Displaying 3 results from an estimated 3 matches for "reversecondcode".
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inversecondcode
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Pretty sure there's nothing wrong with it, but it looks odd in the code.
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++--
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
...U32)
> + return;
> +
> + i->getSrc(t)->getInsn()->dType = TYPE_F32;
> + if (i->src(t).mod != Modifier(0)) {
> + assert(i->src(t).mod == Modifier(NV50_IR_MOD_NOT));
> + i->src(t).mod = Modifier(0);
> + cmp->setCond = reverseCondCode(cmp->setCond);
> + }
> + i->op = OP_MOV;
> + i->setSrc(s, NULL);
> + if (t) {
> + i->setSrc(0, i->getSrc(t));
> + i->setSrc(t, NULL);
> + }
> + }
> + break;
> +
> case OP_SHL:
> {
>...
2014 May 10
1
[PATCH] nv50/ir: make sure to reverse cond codes on all the OP_SET variants
...eephole.cpp
@@ -187,7 +187,8 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
return;
}
- if (insn->op == OP_SET)
+ if (insn->op == OP_SET || insn->op == OP_SET_AND ||
+ insn->op == OP_SET_OR || insn->op == OP_SET_XOR)
insn->asCmp()->setCond = reverseCondCode(insn->asCmp()->setCond);
else
if (insn->op == OP_SLCT)
--
1.8.5.5