Displaying 7 results from an estimated 7 matches for "reversebranchcondition".
2012 Nov 01
0
[LLVMdev] : Predication on SIMD architectures and LLVM
On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote:
> Hi all,
>
> I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we
2017 Jul 09
2
Loop branching inefficiencies in Backend output
Hi,
I am working on a custom backend, and I am trying to figure out how to deal
with some branching inefficiencies in my output code, and the best way to
fix it.
So, let's say I am compiling a small function that takes the sum of an
array.
int loop(int* array, int n) {
int ret = 0;
for (int i = 0; i < n; i++) {
ret += array[i];
}
return ret;
}
The problem I am having is that
2012 Oct 31
3
[LLVMdev] : Predication on SIMD architectures and LLVM
Hi all,
I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this
2006 Jun 03
1
[LLVMdev] Help with pass ordering
Dear llvm guys,
I am trying to add the BreakCriticalEdges pass to my application. I
tried to add it to the PNE pass (e.g. PHIElimination.cpp -
AU.addRequiredID(BreakCriticalEdgesID); ), but I get this error:
llc -f -regalloc=simple Base1Sum.bc -o simple.s
-----------------------------------------------
llc: PassManagerT.h:387: void
llvm::PassManagerT<Trait>::markPassUsed(const
2011 May 02
2
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
...updateTerminator() line 307 of MachineBasicBlock.cpp:
if (FBB) {
// The block has a non-fallthrough conditional branch. If one of its
// successors is its layout successor, rewrite it to a fallthrough
// conditional branch.
if (isLayoutSuccessor(TBB)) {
if (TII->ReverseBranchCondition(Cond))
return;
TII->RemoveBranch(*this);
TII->InsertBranch(*this, FBB, 0, Cond, dl);
} else if (isLayoutSuccessor(FBB)) {
I am investigating an assertion (shown below) that is fired when I run llc
with -march=mipsel -mcpu=4ke. It seems to me that the root caus...
2008 Apr 16
0
[LLVMdev] Being able to know the jitted code-size before emitting
...=====================================================
> --- lib/Target/PowerPC/PPCInstrInfo.h (revision 49716)
> +++ lib/Target/PowerPC/PPCInstrInfo.h (working copy)
> @@ -155,6 +155,11 @@
>
> virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
> virtual bool ReverseBranchCondition(std::vector<MachineOperand>
> &Cond) const;
> +
> + /// GetInstSize - Return the number of bytes of code the specified
> + /// instruction may be. This returns the maximum number of bytes.
> + ///
> + virtual unsigned GetInstSize(const MachineInstr *MI) const;
>...
2008 Apr 15
4
[LLVMdev] Being able to know the jitted code-size before emitting
OK, here's a new patch that adds the infrastructure and the
implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize.
Both functions are virtual functions defined in TargetInstrInfo.h.
For X86, I moved some commodity functions from X86CodeEmitter to
X86InstrInfo.
What do you think?
Nicolas
Evan Cheng wrote:
>
> I think both of these belong to TargetInstrInfo. And