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...de DSA: db85dd66-8b46-43d6-8da3-f12447ed66c6 ==== VECINOS DE ENTRADA ====================================== DC=eadom,DC=ea Default-First-Site-Name\MERCURIO7 v?a RPC GUID del objeto DSA: e644a216-b852-4303-ad3c-09e5733b7233 El ?ltimo intento, efectuado el 2019-11-20 10:29:58, se retras? por una raz?n normal, resultado 8418 (0x20e2): Error en la operaci?n de replicaci?n debido a que no coinciden los esquemas entre los servidores implicados. ?ltima operaci?n correcta efectuada el 2019-11-17 21:45:40. Defau...

Hi, Mips32 has 64 bit floating point instructions, while i64 instructions have to be emulated with i32 instructions. This means that G_LOAD should be custom legalized for s64 integer value, and be legal for s64 floating point value. There are also other generic instructions with the same problem: G_STORE, G_SELECT, G_EXTRACT, and G_INSERT. There are also other configurations where integer

...hineInstr::FastISel) to set the flag. Some passes seem to be stripping the comment flags though. The one I noticed is the pseudo-instruction expansion pass: # *** IR Dump After Machine Copy Propagation Pass ***: # Machine code for function retfloat: Post SSA BB#0: derived from LLVM BB %entry RetRA; comment-flags: FastISel # End machine code for function retfloat. # *** IR Dump After Post-RA pseudo instruction expansion pass ***: # Machine code for function retfloat: Post SSA BB#0: derived from LLVM BB %entry RET %RA # End machine code for function retfloat. > -----Original Mes...

Would adding a flag to MachineInstr::MIFlag do the trick? I'm thinking that fast isel could ensure that a flag (e.g. MIFlag::FastISel) is added to the instructions it creates, then the instruction printer could optionally emit a comment for instructions that have this flag. > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] >

BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; GPRRegs:%vreg0 %vreg1<def> = COPY %vreg0; PTRRegs:%vreg1 GPRRegs:%vreg0 Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg1 RetRA This is what I get. This is what I'd like to get: BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; PTRRegs:%vreg0 Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg0 RetRA On Tue, Aug 25, 2015 at 3:56 PM, Quentin Colombet &...

AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of work to port from one > version to the next though, I did not