Displaying 4 results from an estimated 4 matches for "retops".
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netops
2013 Feb 02
0
[LLVMdev] Moving return value registers from MRI to return instructions
...MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
- for (unsigned i = 0; i != RVLocs.size(); ++i)
- if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
- MRI.addLiveOut(RVLocs[i].getLocReg());
-
SDValue Flag;
-
SmallVector<SDValue, 6> RetOps;
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
// Operand #1 = Bytes To Pop
@@ -1666,6 +1659,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
Flag = Chain.getValue(1);
+ RetOps.push_back(DA...
2008 Feb 27
2
[LLVMdev] 16-bit target problem
Has any one been successful with a 16-bit target? I'm new to LLVM and am
having problems. One problem I found stems from code in
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp: visitRet():
// If this is an integer return value, we need to promote it ourselves to
// the full width of a register, since getCopyToParts and Legalize will use
// ANY_EXTEND rather than sign/zero.
// FIXME:
2009 Feb 11
0
[LLVMdev] Bug in SelectionDAGBuild.cpp?
I'm hitting a problem in SelectionDAGBuild::visitRet(), mainly:
MVT VT = ValueVTs[j];
// FIXME: C calling convention requires the return type to be promoted
to
// at least 32-bit. But this is not necessary for non-C calling
// conventions.
if (VT.isInteger()) {
MVT MinVT = TLI.getRegisterType(MVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
2008 Feb 27
0
[LLVMdev] 16-bit target problem
> // If this is an integer return value, we need to promote it ourselves to
> // the full width of a register, since getCopyToParts and Legalize will use
> // ANY_EXTEND rather than sign/zero.
> // FIXME: C calling convention requires the return type to be promoted to
> // at least 32-bit. But this is not necessary for non-C calling conventions.
> if