Displaying 5 results from an estimated 5 matches for "retopcode".
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getopcode
2007 Aug 09
1
[LLVMdev] Tail call optimization thoughts
...log the two operands of the the tc_return
machine instruction are used to emit code that adjust the
stackpointer and jumps to the tailcallee (either label or register).
Like it is done for EH_RETURN.
in X86RegisterInfo.cpp we would then have
TargetRegisterInfo::emitEpilogue() {
...
if (RetOpcode== X86::TC_RETURN){
if (isDynamicCallee(RetOpCode))
add esp {stack adjustment from tc_return}
jmp {register operand of tc_return}
} else
add esp {stack adjustment from tc_return}
jmp {targetfunction operand}
}
}
resulting code for dynamic function
m...
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
...s i32mem:$dst, i32imm:
$offset),
+// "#TC_RETURN $dst $offset",
+// []>;
+
Why are these needed? They don't look any different from normal add
and subtraction instructions. Why not just use ADJCALLSTACKDOWN and
ADJCALLSTACKUP?
6.
+ } else if (RetOpcode == X86::TCRETURNdi) {
+ // a tailcall adjust the stack
...
+ } else if (RetOpcode == X86::TCRETURNri) {
+ MBBI = prior(MBB.end());
Seems like there are quite a bit of duplicate code between the 2
cases. Please refactor.
7.
X86TargetLowering::X86TargetLowering(TargetMachine &TM)...
2007 Sep 06
2
[LLVMdev] RFC: Tail call optimization X86
Hi Evan,
first off thanks to you and Chris for taking time.
On 6 Sep 2007, at 00:57, Evan Cheng wrote:
> We'd like to see tail call optimization to be similar to the target
> independent lowering of ISD::CALL nodes. These are auto-generated
> from ???CallingConv.td files. Some target specific details such as
> function address register (ECX in your example) should be coded in
2007 Sep 11
2
[LLVMdev] RFC: Tail call optimization X86
...nt delta and the jmp destination of
the call.
The information is used in epilogue generation.
> Why are these needed? They don't look any different from normal add
> and subtraction instructions. Why not just use ADJCALLSTACKDOWN and
> ADJCALLSTACKUP?
>
> 6.
> + } else if (RetOpcode == X86::TCRETURNdi) {
> + // a tailcall adjust the stack
> ...
> + } else if (RetOpcode == X86::TCRETURNri) {
> + MBBI = prior(MBB.end());
>
> Seems like there are quite a bit of duplicate code between the 2
> cases. Please refactor.
Okay dokey
> 7.
> X86TargetLo...
2007 Aug 08
2
[LLVMdev] Destination register needs to be valid after callee saved register restore when tail calling
Hello, Arnold.
> with the sentence i tried to express the question whether there is a
> way to persuade the code generator to use another register to load (or
> move) the function pointer to (right before the callee saved register
> restore) but thinking a little further that's nonsense.
Why don't define some special op for callee address and custom lower it?
I really