Displaying 6 results from an estimated 6 matches for "restricton".
Did you mean:
restriction
2010 Sep 06
2
Strange behavior of interval values in optimize()
Ein eingebundener Text mit undefiniertem Zeichensatz wurde abgetrennt.
Name: nicht verf?gbar
URL: <https://stat.ethz.ch/pipermail/r-help/attachments/20100906/9065ce93/attachment.pl>
2014 Feb 19
2
[LLVMdev] Question about per-operand machine model
Hi JinGu,
We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved.
Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.
2005 Jun 29
2
Postfix / Postini question
I have a mail server that handles several domains. One of these domains has
decided to use Postini. For those not familiar with Postini, you set your MX
records to use their mail servers. They filter mail, and deliver you only the
clean virus/spam free mail. The idea is to only allow incoming mail from their
mail servers so spammers are unable to send to your mail server directly. This
is
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
...gt; ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU)
> STORE dest_reg2, mem (functional unit: LOAD_STORE)
>
> These instructions can be genally packetized together because there is
> no dependency among operands and they use different functional unit. But
> we have one more restricton. The restriction is that some of
> instructions can not access to same register file at the same cycle. In
> other words, if 'src_reg1' of ADD instruction uses register file 'A' and
> 'dest_reg2' of STORE instruction uses same register file at the same
> cycle, i...
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...unctional unit : ALU)
>>> STORE dest_reg2, mem (functional unit: LOAD_STORE)
>>>
>>> These instructions can be genally packetized together because there is
>>> no dependency among operands and they use different functional unit. But
>>> we have one more restricton. The restriction is that some of
>>> instructions can not access to same register file at the same cycle. In
>>> other words, if 'src_reg1' of ADD instruction uses register file 'A' and
>>> 'dest_reg2' of STORE instruction uses same register file a...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...t; STORE dest_reg2, mem (functional unit: LOAD_STORE)
>>>>>
>>>>> These instructions can be genally packetized together because there is
>>>>> no dependency among operands and they use different functional unit. But
>>>>> we have one more restricton. The restriction is that some of
>>>>> instructions can not access to same register file at the same cycle. In
>>>>> other words, if 'src_reg1' of ADD instruction uses register file 'A' and
>>>>> 'dest_reg2' of STORE instruction u...