Displaying 3 results from an estimated 3 matches for "respectl".
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2012 Nov 06
2
[LLVMdev] LLVM IR generation as one of LLVM passes
...re than one such pass).
Is it possible in LLVM? (can I generate IR inside a compilation pass and
use passes in described way?)
If the above description will be not clear, concider following construction
(uppercase letters are passes and lowercase letters are data consumed and
produced by each pass respectlively)
A: file->b
B: b->c
C: b->d
I1: c -> IR
I2: d -> IR
... (other LLVM passes)
and now I could enable passes:
A,B and I1
or
A,C and I2
(both of them generate IR code but differently).
I would be very thankfull if something like that could be done in LLVM and
if yes, any further...
2012 Nov 06
0
[LLVMdev] LLVM IR generation as one of LLVM passes
...Is it possible in LLVM? (can I generate IR inside a compilation pass and use
> passes in described way?)
>
> If the above description will be not clear, concider following construction
> (uppercase letters are passes and lowercase letters are data consumed and
> produced by each pass respectlively)
> A: file->b
> B: b->c
> C: b->d
> I1: c -> IR
> I2: d -> IR
> ... (other LLVM passes)
>
> and now I could enable passes:
> A,B and I1
> or
> A,C and I2
>
> (both of them generate IR code but differently).
>
> I would be very thankfu...
2012 Nov 06
2
[LLVMdev] LLVM IR generation as one of LLVM passes
...rate IR inside a compilation pass and
> use
> > passes in described way?)
> >
> > If the above description will be not clear, concider following
> construction
> > (uppercase letters are passes and lowercase letters are data consumed and
> > produced by each pass respectlively)
> > A: file->b
> > B: b->c
> > C: b->d
> > I1: c -> IR
> > I2: d -> IR
> > ... (other LLVM passes)
> >
> > and now I could enable passes:
> > A,B and I1
> > or
> > A,C and I2
> >
> > (both of them gen...