search for: resourcedelay

...WITH_P1, 0_LATENCY_WITH_P2], [II_MUL]>; >>> >>> where n_LATENCY_WITH_p is defined roughly as: >>> >>> class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> { >>> let Latency = latency; >>> let ResourceDelays = [latency]; >>> } >>> >>> class PR_Pp<int portIdx> : ProcResource<1>; >>> >>> The latency for register write-back/port access is static and without interlock, which I think means the port resources should have 'Buffered = 0' in th...

...t; def :ItinRW<[2_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_MUL]>; > > where n_LATENCY_WITH_p is defined roughly as: > > class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> { > let Latency = latency; > let ResourceDelays = [latency]; > } > > class PR_Pp<int portIdx> : ProcResource<1>; > > The latency for register write-back/port access is static and without interlock, which I think means the port resources should have 'Buffered = 0' in the definition. Is that correct? Yes, but...

...he machine model tables are designed to be efficient for the common case, and per-operand resources don’t really make sense most of the time. It sounds like you want to model the pipeline stage at which a resource is used. To do that with the per-operand machine model (misnomer), I think we need a ResourceDelay vector in addition to ResourceCycles, which we could easily add. However, overall, I think you’re target is interesting enough that you may be better off augmenting the standard machine model with your own model. Your scheduler plugin could keep your own tables or state machine to model the constr...

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them. That’s the only way to get a full reservation table without cu...

>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies. Thanks for your kind explanation. Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of

[I tweaked the subject, #262824 did not introduce the problem, it is just the version I am first seeing this problem] A quick update - I have added 'Sched<[]>' as a base class for all instructions, and also: let hasNoSchedulingInfo = 1; to all the Pseudos, but while most of the errors have gone, I still get the diagnostic for 'COPY' thus: error : No schedule