search for: resource_addr

...e/nvkm/core/device.h b/drm/nouveau/include/nvkm/core/device.h index 7ea8aa7..6bc712f 100644 --- a/drm/nouveau/include/nvkm/core/device.h +++ b/drm/nouveau/include/nvkm/core/device.h @@ -175,6 +175,7 @@ struct nvkm_device_func { void (*fini)(struct nvkm_device *, bool suspend); resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar); resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar); + bool cpu_coherent; }; struct nvkm_device_quirk { diff --git a/drm/nouveau/nouveau_bo.c b/drm/nouveau/nouveau_bo.c index 528bdef..6887d0a 100644 --- a/drm/nouveau/nouveau_bo.c +++ b/dr...

.../nvkm/core/device.h > index 7ea8aa7..6bc712f 100644 > --- a/drm/nouveau/include/nvkm/core/device.h > +++ b/drm/nouveau/include/nvkm/core/device.h > @@ -175,6 +175,7 @@ struct nvkm_device_func { > void (*fini)(struct nvkm_device *, bool suspend); > resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar); > resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar); > + bool cpu_coherent; > }; > > struct nvkm_device_quirk { > diff --git a/drm/nouveau/nouveau_bo.c b/drm/nouveau/nouveau_bo.c > index 528bdef..6887d0a 1...

...if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) /* untiled */ break; - /* fallthrough, tiled memory */ + /* fall through - tiled memory */ case TTM_PL_VRAM: reg->bus.offset = reg->start << PAGE_SHIFT; reg->bus.base = device->func->resource_addr(device, 1); -- 2.20.1

TTM-allocated coherent objects were populated using the DMA API and accessed using the mapping it returned to workaround coherency issues. These issues seem to have been solved, thus remove this extra case to handle and use the regular kernel mapping functions. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nouveau_bo.c | 61

...> index 7ea8aa7..6bc712f 100644 >> --- a/drm/nouveau/include/nvkm/core/device.h >> +++ b/drm/nouveau/include/nvkm/core/device.h >> @@ -175,6 +175,7 @@ struct nvkm_device_func { >> void (*fini)(struct nvkm_device *, bool suspend); >> resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar); >> resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar); >> + bool cpu_coherent; >> }; >> >> struct nvkm_device_quirk { >> diff --git a/drm/nouveau/nouveau_bo.c b/drm/nouveau/nouveau_bo.c >&...

...< NVIF_CLASS_MEM_NV50 || !mem->kind) > /* untiled */ > break; > - /* fallthrough, tiled memory */ > + /* fall through - tiled memory */ > case TTM_PL_VRAM: > reg->bus.offset = reg->start << PAGE_SHIFT; > reg->bus.base = device->func->resource_addr(device, 1); >

...ce_func *func, struct nvkm_subdev *subdev; u64 mmio_base, mmio_size; u32 boot0, strap; - void __iomem *map; + void __iomem *map = NULL; int ret = -EEXIST, i; unsigned chipset; @@ -2961,12 +2961,17 @@ nvkm_device_ctor(const struct nvkm_device_func *func, mmio_base = device->func->resource_addr(device, 0); mmio_size = device->func->resource_size(device, 0); - /* identify the chipset, and determine classes of subdev/engines */ - if (detect) { - map = ioremap(mmio_base, 0x102000); - if (ret = -ENOMEM, map == NULL) + if (detect || mmio) { + map = ioremap(mmio_base, mmio_size); +...

...) diff --git a/drm/nouveau/nvkm/engine/device/pci.c b/drm/nouveau/nvkm/engine/device/pci.c index 62ad0300cfa5..18fab3973ce5 100644 --- a/drm/nouveau/nvkm/engine/device/pci.c +++ b/drm/nouveau/nvkm/engine/device/pci.c @@ -1614,7 +1614,7 @@ nvkm_device_pci_func = { .fini = nvkm_device_pci_fini, .resource_addr = nvkm_device_pci_resource_addr, .resource_size = nvkm_device_pci_resource_size, - .cpu_coherent = !IS_ENABLED(CONFIG_ARM), + .cpu_coherent = !IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64), }; int -- 2.7.2

...break; > - /* fallthrough, tiled memory */ > + /* fall through - tiled memory */ > case TTM_PL_VRAM: > reg->bus.offset = reg->start << PAGE_SHIFT; > reg->bus.base = device->func->resource_addr(device, 1); > -- > 2.20.1 > > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau

...if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) /* untiled */ break; - /* fallthrough, tiled memory */ + /* fall through - tiled memory */ case TTM_PL_VRAM: reg->bus.offset = reg->start << PAGE_SHIFT; reg->bus.base = device->func->resource_addr(device, 1); diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index a97294ac96d5..a12439266bb0 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -4869,10 +4869,12 @@ static void ci_request_link_speed_change_before_state_change(struct...

...) diff --git a/drm/nouveau/nvkm/engine/device/pci.c b/drm/nouveau/nvkm/engine/device/pci.c index 18fab3973ce5..62ad0300cfa5 100644 --- a/drm/nouveau/nvkm/engine/device/pci.c +++ b/drm/nouveau/nvkm/engine/device/pci.c @@ -1614,7 +1614,7 @@ nvkm_device_pci_func = { .fini = nvkm_device_pci_fini, .resource_addr = nvkm_device_pci_resource_addr, .resource_size = nvkm_device_pci_resource_size, - .cpu_coherent = !IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64), + .cpu_coherent = !IS_ENABLED(CONFIG_ARM), }; int diff --git a/lib/include/nvif/os.h b/lib/include/nvif/os.h index 831110904fee..1ed...

.../engine/device/pci.c b/drm/nouveau/nvkm/engine/device/pci.c > index 18fab3973ce5..62ad0300cfa5 100644 > --- a/drm/nouveau/nvkm/engine/device/pci.c > +++ b/drm/nouveau/nvkm/engine/device/pci.c > @@ -1614,7 +1614,7 @@ nvkm_device_pci_func = { > .fini = nvkm_device_pci_fini, > .resource_addr = nvkm_device_pci_resource_addr, > .resource_size = nvkm_device_pci_resource_size, > - .cpu_coherent = !IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64), > + .cpu_coherent = !IS_ENABLED(CONFIG_ARM), > }; > > int > diff --git a/lib/include/nvif/os.h b/lib/inclu...

...break; > - /* fallthrough, tiled memory */ > + /* fall through - tiled memory */ > case TTM_PL_VRAM: > reg->bus.offset = reg->start << PAGE_SHIFT; > reg->bus.base = device->func->resource_addr(device, 1); > diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c > index a97294ac96d5..a12439266bb0 100644 > --- a/drivers/gpu/drm/radeon/ci_dpm.c > +++ b/drivers/gpu/drm/radeon/ci_dpm.c > @@ -4869,10 +4869,12 @@ static void ci_request_link_speed_change_be...

..._ctor(&nvkm_fifo_chan_func, oclass, &chan->object); + + ret = __nvkm_fifo_chan_ctor(func, fifo, size, align, zero, hvmm, push, + engines, oclass, chan); + if (ret) + return ret; + /* determine address of this channel's user registers */ chan->addr = device->func->resource_addr(device, bar) + base + user * chan->chid; @@ -420,3 +533,27 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, nvkm_fifo_cevent(fifo); return 0; } + +int nvkm_fifo_chan_mem_ctor(const struct nvkm_fifo_chan_func *func, + struct nvkm_fifo *fifo, u32 size, u32 align, +...

...ine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index 18fab3973ce5..62ad0300cfa5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c @@ -1614,7 +1614,7 @@ nvkm_device_pci_func = { .fini = nvkm_device_pci_fini, .resource_addr = nvkm_device_pci_resource_addr, .resource_size = nvkm_device_pci_resource_size, - .cpu_coherent = !IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_ARM64), + .cpu_coherent = !IS_ENABLED(CONFIG_ARM), }; int -- 2.8.1.dirty

...if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) /* untiled */ break; - /* fall through - tiled memory */ + fallthrough; /* tiled memory */ case TTM_PL_VRAM: reg->bus.offset = reg->start << PAGE_SHIFT; reg->bus.base = device->func->resource_addr(device, 1); diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 1b383ae0248f..ae3b3002d737 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -331,7 +331,7 @@ nouveau_conn_attach_prop...

...break; > - /* fall through - tiled memory */ > + fallthrough; /* tiled memory */ > case TTM_PL_VRAM: > reg->bus.offset = reg->start << PAGE_SHIFT; > reg->bus.base = device->func->resource_addr(device, 1); > diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c > index 1b383ae0248f..ae3b3002d737 100644 > --- a/drivers/gpu/drm/nouveau/nouveau_connector.c > +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c > @@ -331,7 +331,7 @@...

From: Yonatan Maman <Ymaman at Nvidia.com> This patch series aims to enable Peer-to-Peer (P2P) DMA access in GPU-centric applications that utilize RDMA and private device pages. This enhancement is crucial for minimizing data transfer overhead by allowing the GPU to directly expose device private page data to devices such as NICs, eliminating the need to traverse system RAM, which is the

Changes since last sent: * add a patch to set the device into DRM_SWITCH_POWER_CHANGING state (can be dropped actually, I thought I was needing it, came up with a different approach and forgot to delete it, doesn't hurt though) * expose information about runtime suspending to nvkm so that we can run the pcie workaround only on runtime suspend Karol Herbst (8): pci: disable ASPM

From: Jérôme Glisse <jglisse at redhat.com> (mm is cced just to allow exposure of device driver work without ccing a long list of peoples. I do not think there is anything usefull to discuss from mm point of view but i might be wrong, so just for the curious :)). git://people.freedesktop.org/~glisse/linux branch: nouveau-hmm-v00