search for: reset_control

...E_AUTHOR(DRIVER_AUTHOR); -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_LICENSE("GPL and additional rights"); diff --git a/drm/nouveau_platform.h b/drm/nouveau_platform.h index 58c28b5653d5..ca22c525329a 100644 --- a/drm/nouveau_platform.h +++ b/drm/nouveau_platform.h @@ -28,6 +28,7 @@ struct reset_control; struct clk; struct regulator; +struct platform_driver; struct nouveau_platform_gpu { struct reset_control *rst; @@ -48,4 +49,6 @@ struct nouveau_platform_device { #define nv_device_to_platform(d) \ container_of(d, struct nouveau_platform_devi...

...SCRIPTION(DRIVER_DESC); > -MODULE_LICENSE("GPL and additional rights"); > diff --git a/drm/nouveau_platform.h b/drm/nouveau_platform.h > index 58c28b5653d5..ca22c525329a 100644 > --- a/drm/nouveau_platform.h > +++ b/drm/nouveau_platform.h > @@ -28,6 +28,7 @@ > struct reset_control; > struct clk; > struct regulator; > +struct platform_driver; > > struct nouveau_platform_gpu { > struct reset_control *rst; > @@ -48,4 +49,6 @@ struct nouveau_platform_device { > #define nv_device_to_platform(d) \ &g...

...gpu) +{ + int err; + + err = regulator_enable(gpu->vdd); + if (err) + goto err_power; + + err = clk_prepare_enable(gpu->clk); + if (err) + goto err_clk; + err = clk_prepare_enable(gpu->clk_pwr); + if (err) + goto err_clk_pwr; + clk_set_rate(gpu->clk_pwr, 204000000); + udelay(10); + + reset_control_assert(gpu->rst); + udelay(10); + + err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); + if (err) + goto err_clamp; + udelay(10); + + reset_control_deassert(gpu->rst); + udelay(10); + + return 0; + +err_clamp: + clk_disable_unprepare(gpu->clk_pwr); +err_clk_pwr: + clk_disable_unpr...

This series adds support for probing platform devices on Nouveau, as well as the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since a few extra things need to be supported before that. This version is mostly identical to v2 but fixes an important issue: the drvdata must be set to the drm_device for sysfs to work, so the platform device structure now includes the

...tions(+), 1 deletion(-) diff --git a/drm/nouveau/include/nvkm/core/tegra.h b/drm/nouveau/include/nvkm/core/tegra.h index 16641cec18a2..b5370cb56e3c 100644 --- a/drm/nouveau/include/nvkm/core/tegra.h +++ b/drm/nouveau/include/nvkm/core/tegra.h @@ -11,6 +11,7 @@ struct nvkm_device_tegra { struct reset_control *rst; struct clk *clk; + struct clk *clk_ref; struct clk *clk_pwr; struct regulator *vdd; @@ -36,6 +37,10 @@ struct nvkm_device_tegra_func { * bypassed). A value of 0 means an IOMMU is never used. */ u8 iommu_bit; + /* + * Whether the chip requires a reference clock + */ + bool re...

...+ if (err) > + goto err_power; > + > + err = clk_prepare_enable(gpu->clk); > + if (err) > + goto err_clk; > + err = clk_prepare_enable(gpu->clk_pwr); > + if (err) > + goto err_clk_pwr; > + clk_set_rate(gpu->clk_pwr, 204000000); > + udelay(10); > + > + reset_control_assert(gpu->rst); > + udelay(10); > + > + err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); > + if (err) > + goto err_clamp; > + udelay(10); > + > + reset_control_deassert(gpu->rst); > + udelay(10); > + > + return 0; > + > +err_clamp: > + cl...

This patch series is the final (?) step towards the initial support of GK20A, allowing it to be probed and used (currently at a very slow speed, and for offscreen rendering only) on the Jetson TK1 and Venice 2 boards. The main piece if the first patch which adds platform devices probing support to Nouveau. There are probably lots of things that need to be discussed about it, e.g.: * The way the

These 4 patches fix two issues that existed on Tegra regarding DMA: 1) The bit indicating whether to use an IOMMU or not was hardcoded ; make this a platform property and use it in instmem 2) The DMA mask was not set for platform devices. Fix this by converting more pci_dma* to the DMA API, and use that more generic code to set the DMA mask properly for all platforms. Tested on both x86

This series adds support for probing platform devices on Nouveau, as well as the DT bindings for GK20A. It doesn't enable the GPU yet on Tegra boards since a few extra things need to be supported before that. Thanks to the input received for v1, this version is more self-contained and shares less stuff between nouveau_drm and nouveau_platform. The major change is that nouveau_platform is now

...{ int (*init)(struct host1x_channel *channel, struct host1x *host, unsigned int id); int (*submit)(struct host1x_job *job); + void (*push_wait)(struct host1x_channel *ch, u32 id, u32 thresh); }; struct host1x_cdma_ops { @@ -117,6 +118,8 @@ struct host1x { struct clk *clk; struct reset_control *rst; + u64 fence_ctx_base; + struct iommu_group *group; struct iommu_domain *domain; struct iova_domain iova; @@ -250,6 +253,13 @@ static inline int host1x_hw_channel_submit(struct host1x *host, return host->channel_op->submit(job); } +static inline void host1x_hw_channel_push_w...

From: Thierry Reding <treding at nvidia.com> This set of patches adds support for fences to Tegra DRM and complements the fence FD support for Nouveau. Technically this isn't necessary for a fence-based synchronization loop with Nouveau because the KMS core takes care of all that, but engines behind host1x can use the IOCTL extensions provided here to emit fence FDs that in turn can be

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...p_fb->fb; + return fb; } void rockchip_drm_mode_config_init(struct drm_device *dev) diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6d6da01282f3..f5078e06ad40 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -26,16 +26,10 @@ struct reset_control; -struct tegra_fb { - struct drm_framebuffer base; - struct tegra_bo **planes; - unsigned int num_planes; -}; - #ifdef CONFIG_DRM_FBDEV_EMULATION struct tegra_fbdev { struct drm_fb_helper base; - struct tegra_fb *fb; + struct drm_framebuffer *fb; }; #endif diff --git a/drivers/gpu/drm/teg...

...p_fb->fb; + return fb; } void rockchip_drm_mode_config_init(struct drm_device *dev) diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6d6da01282f3..f5078e06ad40 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -26,16 +26,10 @@ struct reset_control; -struct tegra_fb { - struct drm_framebuffer base; - struct tegra_bo **planes; - unsigned int num_planes; -}; - #ifdef CONFIG_DRM_FBDEV_EMULATION struct tegra_fbdev { struct drm_fb_helper base; - struct tegra_fb *fb; + struct drm_framebuffer *fb; }; #endif diff --git a/drivers/gpu/drm/teg...

...p_fb->fb; + return fb; } void rockchip_drm_mode_config_init(struct drm_device *dev) diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6d6da01282f3..f5078e06ad40 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -26,16 +26,10 @@ struct reset_control; -struct tegra_fb { - struct drm_framebuffer base; - struct tegra_bo **planes; - unsigned int num_planes; -}; - #ifdef CONFIG_DRM_FBDEV_EMULATION struct tegra_fbdev { struct drm_fb_helper base; - struct tegra_fb *fb; + struct drm_framebuffer *fb; }; #endif diff --git a/drivers/gpu/drm/teg...