search for: reserveresourc

...2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTr...

...strStage<1, [ALU1, ALU2]>]> > > I want to express that there are two ALU's, and four bundle slots, and > in this case while allocating this type of instructions several times, > I would like to be allowed only two such instructions per cycle. > > ResourceTracker->reserveResources(); > > ResourceTracker->reserveResources(); > > ResourceTracker->reserveResources(); > > ResourceTracker->reserveResources(); > > ResourceTracker->reserveResources(); > > DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const > llvm::M...

...InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTrans) !...

...InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTrans) !...

...InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTrans) !...

For some reason on my VLIW target DFAPacketizer fails at assert(CachedTable.count(StateTrans) != 0); in the following function: // reserveResources - Reserve the resources occupied by a MCInstrDesc and // change the current state to reflect that change. void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); uns...

...trying to get the DFAPacketizer to work for my target but with any > instruction I get the > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes > out before packeting a single instruction. Do you reserve some resource without verification? Note that reserveResources() should be called iff canReserveResources() is true (the call order is important here) even for the trivial case (0 instructions in the packet). See VLIWPacketizerList as an example on how to use the API's. Ivan > > I have a *GenDFAPacketizer.inc file and my packetizer pass checks...

Hi, I'm trying to get the DFAPacketizer to work for my target but with any instruction I get the 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes out before packeting a single instruction. I have a *GenDFAPacketizer.inc file and my packetizer pass checks that the table is not empty before proceeding. I also have a schedule file with my functional

...k for my target but with any > > instruction I get the > > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it > crashes > > out before packeting a single instruction. > > Do you reserve some resource without verification? > > Note that reserveResources() should be called iff canReserveResources() > is true (the call order is important here) even for the trivial case (0 > instructions in the packet). See VLIWPacketizerList as an example on how > to use the API's. > > Ivan > > > > > I have a *GenDFAPacketizer.inc...

...;> > instruction I get the >> > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and >> it crashes >> > out before packeting a single instruction. >> >> Do you reserve some resource without verification? >> >> Note that reserveResources() should be called iff canReserveResources() >> is true (the call order is important here) even for the trivial case (0 >> instructions in the packet). See VLIWPacketizerList as an example on how >> to use the API's. >> >> Ivan >> >> > >> &gt...

...>> class MachineLoopInfo; >> class MachineDominatorTree; >> class InstrItineraryData; >> -class ScheduleDAGInstrs; >> +class DefaultVLIWScheduler; >> class SUnit; >> >> class DFAPacketizer { >> @@ -77,6 +78,8 @@ public: >> // reserveResources - Reserve the resources occupied by a machine >> // instruction and change the current state to reflect that change. >> void reserveResources(llvm::MachineInstr *MI); >> + >> + const InstrItineraryData *getInstrItins() const { return InstrItins; } >> }; &g...