search for: reservedregs

...problem should not be the erroneous over-writing of a live preg.) Also, I'm confused about the code that gets a preg for a given vreg. Previously,you gave me code that takes into account the "allocation order" and the "reserved regs", including the following: BitVector reservedRegs = TRI->getReservedRegs(Fn); ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); while (rItr != rawOrder.end()) { while (rItr != rawOrder.end() && reservedRegs.test(*rIt...

...e following code: %a1<def> = COPY %a0<kill> ... %a0h<def> = COPY %a1l , as input to MachineCopyPropagation. The second copy is illegally erased! This is wrong, because it is the low part of a1 that is copied to the high part of a0. At a first glance, it seems that if (!ReservedRegs.test(Def) && (!ReservedRegs.test(Src) || NoInterveningSideEffect(CopyMI, MI)) && (SrcSrc == Def || TRI->isSubRegister(SrcSrc, Def))) { ... (erase COPY) , should be extended to ... (SrcSrc == Def || (TRI->isSubRegister(SrcSrc, Def) &&...

Hi Susan, Jakob just pointed me to 'MachineOperand::substPhysReg(unsigned preg, const TargetRegisterInfo& TRI)'. That substitutes the given physreg for a virtreg operand, taking the subregister index into account. That is what my examples have been doing manually. Using substPhysReg would allow you to tidy the Gcra code up slightly. - Lang. On Thu, Nov 15, 2012 at 11:21 AM, Lang

Thanks Jakob. I should have mentioned that earlier. :) When you see mismatched sizes on operands it's a fair bet that the subreg rewriting has gone wrong. I should have pulled that entirely out of the preg search loop in the previous example. Fixed version attached. - Lang. -------------- next part -------------- An HTML attachment was scrubbed... URL:

...y. In short: > > int regClass = MRI->getRegClass(vreg)->getID(); > const TargetRegisterClass *trc = TRI->getRegClass(regClass); > ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); > ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); > while (reservedRegs.test(*rItr)) > ++rItr; > preg = *rItr; > > Alternatively, you could use the AllocationOrder class > (lib/CodeGen/AllocationOrder.h). This has the benefit of considering > register hints for improved coalescing too. It does, however, require you > to use VirtRegMap. > >...

...ere I do this somewhat manually. In short: int regClass = MRI->getRegClass(vreg)->getID(); const TargetRegisterClass *trc = TRI->getRegClass(regClass); ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); while (reservedRegs.test(*rItr)) ++rItr; preg = *rItr; Alternatively, you could use the AllocationOrder class (lib/CodeGen/AllocationOrder.h). This has the benefit of considering register hints for improved coalescing too. It does, however, require you to use VirtRegMap. Hope this helps! Cheers, Lang. On Wed,...

...lass = MRI->getRegClass(vreg)->getID(); >> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); >> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >> while (reservedRegs.test(*rItr)) >> ++rItr; >> preg = *rItr; >> >> Alternatively, you could use the AllocationOrder class >> (lib/CodeGen/AllocationOrder.h). This has the benefit of >> considering register hints for improved coalescing too. It does, >>...

...t;> int regClass = MRI->getRegClass(vreg)->getID(); >> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); >> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >> while (reservedRegs.test(*rItr)) >> ++rItr; >> preg = *rItr; >> >> Alternatively, you could use the AllocationOrder class >> (lib/CodeGen/AllocationOrder.h). This has the benefit of considering >> register hints for improved coalescing too. It does, however, require you >>...

...ly. In short: > > int regClass = MRI->getRegClass(vreg)->getID(); > const TargetRegisterClass *trc = TRI->getRegClass(regClass); > ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); > ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); > while (reservedRegs.test(*rItr)) > ++rItr; > preg = *rItr; > > Alternatively, you could use the AllocationOrder class > (lib/CodeGen/AllocationOrder.h). This has the benefit of considering > register hints for improved coalescing too. It does, however, require > you to use VirtRegMap. > &g...

...->getID(); >>> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn); >>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >>> while (reservedRegs.test(*rItr)) >>> ++rItr; >>> preg = *rItr; >>> >>> Alternatively, you could use the AllocationOrder class >>> (lib/CodeGen/AllocationOrder.h). This has the benefit of >>> considering register hints for i...

...>>> const TargetRegisterClass *trc = TRI->getRegClass(regClass); >>>> ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn)**; >>>> ArrayRef<uint16_t>::iterator rItr = rawOrder.begin(); >>>> while (reservedRegs.test(*rItr)) >>>> ++rItr; >>>> preg = *rItr; >>>> >>>> Alternatively, you could use the AllocationOrder class >>>> (lib/CodeGen/AllocationOrder.**h). This has the benefit of >>>> consid...

Hi Susan, Sorry for the delayed response. Thanks for the test cases - I'm looking in to this now. - Lang. On Mon, Nov 5, 2012 at 2:58 PM, Susan Horwitz <horwitz at cs.wisc.edu> wrote: > Hi Lang, > > I looked more into one of the problems I'm now having, and I've attached 3 > files: > > Gcra.cpp is like your version except that for two specific vregs it uses

Hi Lang, I looked more into one of the problems I'm now having, and I've attached 3 files: Gcra.cpp is like your version except that for two specific vregs it uses hard-coded pregs instead of the first in the corresponding class. bug1.c is an input that causes the failed assertion for me. If I use the non-debug version of LLVM-3.1 I instead get assembler errors like this: Error: