Displaying 4 results from an estimated 4 matches for "reserve_reg".
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
..._X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_W %T1_Z %T1_Y %T1_X
%vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3
%vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2
%vreg1<def> = COPY %T1_Z; R600_TReg32:%vreg1
%vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0
RESERVE_REG 0
%vreg4<def> = FNEG_R600 %vreg3; R600_Reg32:%vreg4 R600_TReg32:%vreg3
%vreg5<def> = MOV_IMM_F32 0.000000e+00; R600_Reg32:%vreg5
%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
%vreg7<de...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...; R600_Reg128:%vreg19,%vreg20 R600_TReg32:%vreg14
%vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2
%vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
%vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18
RESERVE_REG 0
%vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15
%vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2
%vreg25<def> = R600_LOAD_CONST 6; R600_R...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...9,%vreg20 R600_TReg32:%vreg14
> %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2
> %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22
> %vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18
> RESERVE_REG 0
> %vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15
> %vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2
> %vreg25<def> = R600_LOAD_...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...===//
> +
> +let TargetPrefix = "AMDGPU", isTarget = 1 in {
> +
> + def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], [IntrNoMem]>;
> + def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
> +
> + def int_AMDGPU_arl :...