Displaying 3 results from an estimated 3 matches for "rescheduleop".
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rescheduleops
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
I have two questions regarding MachineMemOperands and dependence
information.
Q1) I noticed that MachineMemOperands are lost when two LDRs are combined
and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
(before optimization)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
%reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0;
mem:LD4[%uglygep2021]
(after optimization)
%reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264,...
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote:
> I have two questions regarding MachineMemOperands and dependence information.
>
> Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
>
> (before optimization)
> %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10]
> %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021]
>
> (after optimization)
> %reg1054<def>, %reg1033<de...
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
...n Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote:
>
> > I have two questions regarding MachineMemOperands and dependence
> information.
> >
> > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined
> and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
> >
> > (before optimization)
> > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
> mem:LD4[%uglygep10]
> > %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0;
> mem:LD4[%uglygep2021]
> >
> > (after optimization)
&g...