search for: replaceallusesofvaluewith

...Chain, Ptr, LD->getPointerInfo(), MVT::i32, LD->isVolatile(), LD->isNonTemporal(), LD->getAlignment()); Chain = LdResult.getValue(1); SDValue Mask = DAG.getConstant(0x1, MVT::i32); DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 0), LdResult); DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), Chain); DAG.RemoveDeadNode(LD); //return DAG.getNode(ISD::AND, dl, MVT::i32, Op, Mask); } } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/l...

...n MergeConsecutiveStores. Two 16bit loads have been merged to one 32bit load, and two 16bit stores have been combined to one 32bit store. And then the code goes like this: // Replace one of the loads with the new load. LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), SDValue(NewLoad.getNode(), 1)); // Remove the rest of the load chains. for (unsigned i = 1; i < NumElem ; ++i) { // Replace all chain users of the old load nodes with the chain of the new // load node. LoadSDNode *Ld = cast&...

...>> TheXor->dump(&DAG); >> dbgs()<< "\nWith: "; >> Tmp.getNode()->dump(&DAG); >> dbgs()<< '\n'); >> WorkListRemover DeadNodes(*this); >> DAG.ReplaceAllUsesOfValueWith(N1, Tmp,&DeadNodes); >> removeFromWorkList(TheXor); >> DAG.DeleteNode(TheXor); >> return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), >> MVT::Other, Chain, Tmp, N2); >> } >> } >> >&g...

...t, and further simplified by hand.    The problem did not occur in 2.8. > (Removing the trivial branch makes the problem go away.) > > I'm not sure where to begin debugging it, so any pointers would be appreciated. DAGCombiner::visitADDE looks suspicious to me... specifically, the way ReplaceAllUsesOfValueWith is used. -Eli

...to the llvm.opencl.other.get.global.id(0x002ED3E0) node so that I can completely remove the load, undef, and targetglobaladdress nodes. If anyone can give me any hints on how I can do this, it would be greatly appreciated. I am already creating a target specific constant and then using DAG->ReplaceAllUsesOfValueWith(Op, SDValue(N, 0)) to remove the first connect, but I'm not sure how to remove the chain. Thanks for your time, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20090604/a4ba9bfc/attachment.html...

In both LLVM 2.9 and the current svn head, I get the following error when running llc % llc < fxp2.ll LLVM ERROR: Cannot select: 0xa5302b0: glue = carry_false [ID=7] on this code: target triple = "i386-pc-linux-gnu" define i32 @fxpadd(i32 %cl) { entry: %0 = zext i32 %cl to i128 %1 = zext i32 %cl to i128 %2 = add i128 %1, %0 br label %L1001510 L1001510:

> As far as I know, you cannot define a tablegen pattern with multiple results, and need to use C++ matching. I’m kind of surprised there are defined td nodes for these. Yes they were added a while ago, but never used. If I write a C++ matcher, will the register allocator work correctly? The multiplication instruction I'm working with always writes the result to registers `R1` and `R0`,

...DEBUG(dbgs() << "\nReplacing.8 "; TheXor->dump(&DAG); dbgs() << "\nWith: "; Tmp.getNode()->dump(&DAG); dbgs() << '\n'); WorkListRemover DeadNodes(*this); DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); removeFromWorkList(TheXor); DAG.DeleteNode(TheXor); return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), MVT::Other, Chain, Tmp, N2); } } if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() !...

...; "\nReplacing.8 "; > TheXor->dump(&DAG); > dbgs() << "\nWith: "; > Tmp.getNode()->dump(&DAG); > dbgs() << '\n'); > WorkListRemover DeadNodes(*this); > DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); > removeFromWorkList(TheXor); > DAG.DeleteNode(TheXor); > return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), > MVT::Other, Chain, Tmp, N2); > } > } > > if (Op0.getOpcode() != ISD::S...

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >

...sses at all], it takes the same amount of time. The time is spent in 12.94% lacsap lacsap [.] llvm::SDNode::use_iterator::operator== 7.68% lacsap lacsap [.] llvm::SDNode::use_iterator::operator* 7.53% lacsap lacsap [.] llvm::SelectionDAG::ReplaceAllUsesOfValueWith 7.28% lacsap lacsap [.] llvm::SDNode::use_iterator::operator++ 5.59% lacsap lacsap [.] llvm::SDNode::use_iterator::operator!= 4.65% lacsap lacsap [.] llvm::SDNode::hasNUsesOfValue 3.82% lacsap lacsap [.] llvm::SDUse::ge...

I've definitely "run into this problem", and I would very much love to remove my kludges [that are incomplete, because I keep finding places where I need to modify the code-gen to "fix" the same problem - this is probably par for the course from a complete amateur compiler writer and someone that has only spent the last 14 months working (as a hobby) with LLVM]. So whilst