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Hal, that’s a good point. There are more manually-maintained tables in the X86 backend that should probably be tablegened: the memory-folding tables and ReplaceableInstrs, to name a couple. If you have ideas on how to get these auto-generated, please let us know. From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Hal Finkel via llvm-dev Sent: Wednesday, November 23, 2016 15:01 To: Haber, Gadi <gadi.haber at intel.com> Cc: llvm-dev at list...

...ps.com> wrote: > Is there a simple way to just change the opcode of a machine instruction. > > I have a lot of long/short pairs where when I know the offset, i can > replace the long version with the short version. > Hey Reed, The x86 target does something like this. Check out ReplaceableInstrs inlib/Target/X86/X86InstrInfo.cpp. Hope that helps, Cameron -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130213/09a36415/attachment.html>

Is there a simple way to just change the opcode of a machine instruction. I have a lot of long/short pairs where when I know the offset, i can replace the long version with the short version. Tia. REed

Hi All. This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible. When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of