Displaying 3 results from an estimated 3 matches for "remlatency".
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getlatency
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
...reg9
SReg_32: 45 > 44(+ 0 livethru)
VS_32: 51 > 18(+ 0 livethru)
Ready @46c
HWLGKM +1x105u
TopQ.A BotLatency SU(43) 78c
*** Max MOps 1 at cycle 46
Cycle: 47 TopQ.A
TopQ.A @47c
Retired: 47
Executed: 47c
Critical: 47c, 47 MOps
ExpectedLatency: 10c
- Latency limited.
BotQ.A RemLatency SU(1698) 99c
TopQ.A + Remain MOps: 1692
TopQ.A RemLatency SU(201) 97c
BotQ.A + Remain MOps: 1647
BotQ.A: 1698 1694 1695
Here is example debugging output which. Where is the cycle time
here?
> BTW- I just checked in a small fix for in-order scheduling that might make debugging this easie...
2016 Oct 28
2
mischeduler
...once per cycle, in contrast to what the comment
suggests.
...
// Schedule aggressively for latency in PostRA mode. We don't check for
// acyclic latency during PostRA, and highly out-of-order processors will
// skip PostRA scheduling.
if (!OtherResLimited) {
if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() >
Rem.CriticalPath)) {
Policy.ReduceLatency |= true;
Why !OtherResLimited? tryCandidate() has already checked for resource
balancing just
before this. To not do the latency check then only means falling back to
original
order.
/Jonas
2015 Mar 27
2
[LLVMdev] Question about load clustering in the machine scheduler
Hi,
I have a program with over 100 loads (each with a 10 cycle latency)
at the beginning of the program, and I can't figure out how to get
the machine scheduler to intermix ALU instructions with the loads to
effectively hide the latency.
It seems the issue is with load clustering. I restrict load clustering
to 4 at a time, but when I look at the debug output, the loads are
always being