Displaying 3 results from an estimated 3 matches for "rematerializetrivialdef".
2020 Jun 16
2
[ARM] Thumb code-gen for 8-bit imm arguments results in extra reg copies
...gpr, dead $cpsr = tMOVi8 20, 14, $noreg
$r0 = COPY %0:tgpr
$r1 = COPY %1:tgpr
IIUC, there are a couple of reasons why this happens:
(a) tMOVi8 pattern isn't marked with isRematerializable, isAsCheapAsMove,
and isMoveImm.
(b) After annotating the pattern with above flags,
RegisterCoalescer::reMaterializeTrivialDef still bails out because
the above assignment has 2 definitions, with only one live definition.
To address this issue, I attached a hackish patch that
(a) Marks tMOVi8 pattern with:
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1
I am not sure if this is entirely correct ?
(b) Modi...
2020 Jun 18
2
[ARM] Thumb code-gen for 8-bit imm arguments results in extra reg copies
On Tue, 16 Jun 2020 at 15:47, Tim Northover <t.p.northover at gmail.com> wrote:
>
> On Tue, 16 Jun 2020 at 10:23, Prathamesh Kulkarni via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > (b) Modifies RegisterCoalescer::reMaterializeTrivialDef and
> > TargetInstrInfo::isReallyTriviallyReMaterializableGeneric to check
> > for single live def, instead of single def.
>
> This seems dodgy to me. The instruction does also change CPSR so for
> the transformation to be valid you have to know that register is dead
> where...
2011 May 06
0
[LLVMdev] Question about linking llvm-mc when porting a new backend
...llvm::CriticalAntiDepBreaker::ScanInstruction(llvm::MachineInstr*,
unsigned int)in libLLVMCodeGen.a(CriticalAntiDepBreaker.cpp.o)
llvm::CriticalAntiDepBreaker::PrescanInstruction(llvm::MachineInstr*)
in libLLVMCodeGen.a(CriticalAntiDepBreaker.cpp.o)
llvm::SimpleRegisterCoalescing::ReMaterializeTrivialDef(llvm::LiveInterval&,
unsigned int, unsigned int, llvm::MachineInstr*)in
libLLVMCodeGen.a(SimpleRegisterCoalescing.cpp.o)
llvm::SimpleRegisterCoalescing::ReMaterializeTrivialDef(llvm::LiveInterval&,
unsigned int, unsigned int, llvm::MachineInstr*)in
libLLVMCodeGen.a(SimpleRegisterCoalescing...