Displaying 11 results from an estimated 11 matches for "rem_len".
2007 Feb 24
2
SHA256 password patch
Hi,
I made a patch against branch-1.0 for SHA256 password hashing support
for Dovecot.
Courier Authlib supports this hashing scheme and in order to migrate
from Courier to Dovecot, I've added SHA256 support to Dovecot.
The attached patch is based on BSD licensed code from Olivier Gay
(http://www.ouah.org/ogay/sha2/).
Changes made by me in Olivier's sha2{.h,.c} code:
- Prototype for
2013 Aug 02
1
[PATCH 3/5] Intel MIC Host Driver Changes for Virtio Devices.
...> > + return next;
> > +}
> > +
> > +/*
> > + * Central API which initiates the copies across the PCIe bus.
> > + */
> > +static int mic_virtio_copy_desc_buf(struct mic_vdev *mvdev,
> > + struct vring_desc *desc,
> > + void __user *ubuf, u32 rem_len, u32 doff, u32 *out_len)
> > +{
> > + void __iomem *dbuf;
> > + int err;
> > + u32 len = le32_to_cpu(desc->len);
> > + u16 flags = le16_to_cpu(desc->flags);
> > + u64 addr = le64_to_cpu(desc->addr);
> > +
> > + dbuf = mvdev->mdev->aper....
2013 Aug 02
1
[PATCH 3/5] Intel MIC Host Driver Changes for Virtio Devices.
...> > + return next;
> > +}
> > +
> > +/*
> > + * Central API which initiates the copies across the PCIe bus.
> > + */
> > +static int mic_virtio_copy_desc_buf(struct mic_vdev *mvdev,
> > + struct vring_desc *desc,
> > + void __user *ubuf, u32 rem_len, u32 doff, u32 *out_len)
> > +{
> > + void __iomem *dbuf;
> > + int err;
> > + u32 len = le32_to_cpu(desc->len);
> > + u16 flags = le16_to_cpu(desc->flags);
> > + u64 addr = le64_to_cpu(desc->addr);
> > +
> > + dbuf = mvdev->mdev->aper....
2018 Nov 03
0
[PATCH 1/1] Add vhost_blk driver
...8 u8 status;
139
140 if ((type == VIRTIO_BLK_T_IN) || (type == VIRTIO_BLK_T_OUT)) {
141 bool write = (type == VIRTIO_BLK_T_OUT);
142 int nr_seg = (write ? req->out_num : req->in_num) - 1;
143 unsigned long sector = le64_to_cpu(req->hdr.sector);
144 ssize_t len, rem_len;
145
146 if (!req->q->blk->backend) {
147 vq_err(vq, "blk %p no backend!\n", req->q->blk);
148 ret = -EINVAL;
149 goto out_err;
150 }
151
152 len = iov_length(&vq->iov[1], nr_seg);
> 153 pr_debug("%s: [pid:%d %s] %s...
2013 Jul 25
1
[PATCH 3/5] Intel MIC Host Driver Changes for Virtio Devices.
...SC_F_NEXT))
+ return -1U;
+ next = le16_to_cpu(desc->next);
+ read_barrier_depends();
+ return next;
+}
+
+/*
+ * Central API which initiates the copies across the PCIe bus.
+ */
+static int mic_virtio_copy_desc_buf(struct mic_vdev *mvdev,
+ struct vring_desc *desc,
+ void __user *ubuf, u32 rem_len, u32 doff, u32 *out_len)
+{
+ void __iomem *dbuf;
+ int err;
+ u32 len = le32_to_cpu(desc->len);
+ u16 flags = le16_to_cpu(desc->flags);
+ u64 addr = le64_to_cpu(desc->addr);
+
+ dbuf = mvdev->mdev->aper.va + addr + doff;
+ *out_len = min_t(u32, rem_len, len - doff);
+ if (flags &...
2013 Jul 25
1
[PATCH 3/5] Intel MIC Host Driver Changes for Virtio Devices.
...SC_F_NEXT))
+ return -1U;
+ next = le16_to_cpu(desc->next);
+ read_barrier_depends();
+ return next;
+}
+
+/*
+ * Central API which initiates the copies across the PCIe bus.
+ */
+static int mic_virtio_copy_desc_buf(struct mic_vdev *mvdev,
+ struct vring_desc *desc,
+ void __user *ubuf, u32 rem_len, u32 doff, u32 *out_len)
+{
+ void __iomem *dbuf;
+ int err;
+ u32 len = le32_to_cpu(desc->len);
+ u16 flags = le16_to_cpu(desc->flags);
+ u64 addr = le64_to_cpu(desc->addr);
+
+ dbuf = mvdev->mdev->aper.va + addr + doff;
+ *out_len = min_t(u32, rem_len, len - doff);
+ if (flags &...
2018 Nov 02
0
[PATCH 1/1] Add vhost_blk driver
...;
> + u8 status;
> +
> + if ((type == VIRTIO_BLK_T_IN) || (type == VIRTIO_BLK_T_OUT)) {
> + bool write = (type == VIRTIO_BLK_T_OUT);
> + int nr_seg = (write ? req->out_num : req->in_num) - 1;
> + unsigned long sector = le64_to_cpu(req->hdr.sector);
> + ssize_t len, rem_len;
> +
> + if (!req->q->blk->backend) {
> + vq_err(vq, "blk %p no backend!\n", req->q->blk);
> + ret = -EINVAL;
> + goto out_err;
> + }
> +
> + len = iov_length(&vq->iov[1], nr_seg);
> + pr_debug("%s: [pid:%d %s] %s sector %lld...
2020 Sep 25
20
[RFC PATCH 00/19] vhost-user-rpmb (Replay Protected Memory Block)
Hi,
This is an initial implementation of a vhost-user backend for the
VirtIO RPMB device. The device is currently in the draft of the next
VirtIO specification and describes block device which uses combination
of a key, nonce, hashing and a persistent write counter to prevent
replay attacks (hence Replay Protected Memory Block).
It is implemented as a vhost-user device because we want to
2013 Jul 29
0
[PATCH 3/5] Intel MIC Host Driver Changes for Virtio Devices.
...sc->next);
> + read_barrier_depends();
> + return next;
> +}
> +
> +/*
> + * Central API which initiates the copies across the PCIe bus.
> + */
> +static int mic_virtio_copy_desc_buf(struct mic_vdev *mvdev,
> + struct vring_desc *desc,
> + void __user *ubuf, u32 rem_len, u32 doff, u32 *out_len)
> +{
> + void __iomem *dbuf;
> + int err;
> + u32 len = le32_to_cpu(desc->len);
> + u16 flags = le16_to_cpu(desc->flags);
> + u64 addr = le64_to_cpu(desc->addr);
> +
> + dbuf = mvdev->mdev->aper.va + addr + doff;
> + *out_len = min_...
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after