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> Longer term, I hope to improve the fence elimination of the ARM backend with > a kind of PRE algorithm. Both of these improvements to the ARM backend > should be fairly straightforward to port to the POWER architecture later, > and I hope to also do that. > > Any reason these couldn't be done at the IR level? I definitely agree here. At the time, it was a plausible idea

...gt; in a target-independent and a target-dependent file: the current pass claims > to be target-independent but is actually designed for ARM: for example it > puts a release-fence before a seq_cst CAS, which would be unsound on Power > if the backend was more agressive and using lwsync for release_fences. I don't know the Power architecture, but this failure ought to be describable in terms of LLVM's own memory model (if a valid Power implementation of LLVM IR can trigger it, then the transformation itself is wrong). Do you have an example execution in mind that shows it? > Since...