search for: relaxinstruct

...struction takes a register as operand and can therefore jump to any 32-bit address. In AsmBackend, there are methods for relaxing instructions, that I wanted to use to replace "JCC imm9" instructions with a sequence of instructions that jumps further. However, I have two questions: - relaxInstruction does not seem to be able to replace one instruction with a sequence of instructions - I've looked at many other LLVM backends (AVR, ARC, ARM, MIPS and RISC-V), and none of them really seem to do interesting things in relaxInstruction. ARM for instance relaxes Thumb instructions to normal...

...nverted one plus jump to make the branch possible. The range of unconditional jump is 1MiB. It looks like ########################## bne a0, a1, FAR_BRANCH … FAR_BRANCH: converted to ########################## beq a0, a1, SKIP_J j FAR_BRANCH SKIP_J: … FAR_BRANCH: I found there is a target hook, relaxInstruction, that tries to achieve the similar goal. However, the target hook only replaces one MCInst with another one with a larger branch range. For example, c.beqz will be converted to beq in the RISC-V backend if the fixup value is out of range. There seems no target hook to convert one MCInst to a com...

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to

...###################### > bne a0, a1, FAR_BRANCH > … > FAR_BRANCH: > > converted to > > ########################## > beq a0, a1, SKIP_J > j FAR_BRANCH > SKIP_J: > … > FAR_BRANCH: > > I found there is a target hook, relaxInstruction, that tries to > achieve the similar goal. However, the target hook only replaces > one MCInst with another one with a larger branch range. For > example, c.beqz will be converted to beq in the RISC-V backend if > the fixup value is out of range. There seems no target...

On Fri, 2015-02-20 at 13:47 -0500, Rafael Espíndola wrote: > > Your task, should you choose to accept it, is to make it cope with other > > forms of relaxation where necessary. > > And if not, please open a bug :-) http://llvm.org/bugs/show_bug.cgi?id=22662 FWIW I could reproduce the 'movl foo, %ebx' one but a relative jump *was* using 16 bits (although gas uses 8):

...e instruction in 32-bit mode if it finds it doesn't > fit? > > Do we just need to support a similar fixup for promoting 16-bit to > 32-bit relocations? OK, the term I was looking for was 'relaxation'. Look in lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp for X86AsmBackend::relaxInstruction() and related methods. Observe that it will cope with 'relaxing' 8-bit PC-relative relocations to 32-bit PC-relative, but it doesn't cope with anything else. Your task, should you choose to accept it, is to make it cope with other forms of relaxation where necessary. Note that the...

On 20.02.2015 16:38, David Woodhouse wrote: > On Fri, 2015-02-20 at 15:58 +0100, Vladimir 'φ-coder/phcoder' Serbinenko > wrote: >> When experimenting with compiling GRUB2 with clang using integrated as, >> I found out that it generates a 16-bit code bigger than gas counterpart >> and result gets too big for size constraints of bootsector. This was >> traced

...e, + bool &IsResolved) { + AArch64AsmBackend::processFixupValue(Asm, Layout, Fixup, DF, Target, Value, + IsResolved); + if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_call) + IsResolved = false; + } + void relaxInstruction(const MCInst &, llvm::MCInst &) const { + llvm_unreachable("Cannot relax instructions"); + } + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { + // This table *must* be in...