Displaying 1 result from an estimated 1 matches for "relaxedopcode".
2014 Nov 13
2
[LLVMdev] [RFC] TableGen help for relaxation
...) Target instructions optionally set RelaxedInstr, as in:
def JMP32 : Instruction<stuff>; // no relaxation from here
def JMP8 : Instruction<stuff> {
let RelaxedInstr = JMP32; // relax to 32-bit jmp
}
3) The tblgen -gen-instr-info processor uses RelaxedInstruction to
create the RelaxedOpcode field for the corresponding MCInst. The
RelaxedOpcode field contains the target specific opcode (an
enumeration value) of the specified RelaxedInstr.
4) From C++, targets access the RelaxedOpcode field as needed, akin to
TSFlags. This eliminates the headaches of massive opcode switch
statements...