search for: relaxation

...used with filetype=obj, relax all fixups in the emitted object file It also appears in clang: -mrelax-all (integrated-as) Relax all machine instructions I'd like to discuss the naming and semantics of this flag, because ISTM at least the name is misleading. If I understand correctly, relaxation is always required in MC (*) to produce correct code, and in fact MC always performs relaxation, whether mc-relax-all was passed or not. What mc-relax-all seems to affect is how certain decisions in MC are handled. Specifically: * Whether MC tries to understand if a fixup requires relaxing prior t...

Hi Eli, It's more of a debugging tool and stress test of the x86 branch relaxation than anything. It's definitely not intended to be an optimization. "relax-all" says to not just relax instructions that are strictly required, but to relax every instruction that can be relaxed, whether it's needed or not. I'm more inclined to remove the command line options...

Hello LLVM, My target has a complex relaxation hierarchy. Perhaps a modest TableGen extension would help consolidate most of the work involved in choosing a relaxed opcode. I also notice the x86 relaxation code with a comment wondering if TableGen could improve life. Does the following outline sound interesting? 1) Add a new field of type &...

Hi, Does lld support linker relaxation that may shrink code size? As far as I see lld seems to assume that the content of input sections to be fixed other than patching up relocations, but I believe some targets may benefit the extra optimization opportunity with relaxation. Specifically, I'm currently working on adding support for...

Hi all, clang -O0 currently differs from -O1 and higher in passing down -mrelax-all. When compiling assembler files, this results in conditional jumps using the relaxed forms, which is surprising. Based on the discussion on IRC, I did a llvm/clang release build with -O0 for OPTIMIZER and -O0 -mno-relax-all. Result is: -O0 (-mrelax-all) 68m27.893s 254m19.920s 1m45.720s -O0 -mno-relax-all

> > It's more of a debugging tool and stress test of the x86 branch relaxation than anything. It's definitely not intended to be an optimization. > > "relax-all" says to not just relax instructions that are strictly required, but to relax every instruction that can be relaxed, whether it's needed or not. > > I'm more inclined to remove the co...

...due to the other changes. On Tue, Jul 11, 2017 at 1:59 PM, Peter Smith via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hello, > > To the best of my knowledge I think the closest analogue is something > like the Synthetic EHFrame and MergeInputSections, not strictly code > relaxation, but these do involve changes in size of sections. > > Can I ask you a quick question? In many architectures not all > pc-relative offsets are exposed to the linker as relocations so it > isn't safe to change the sizes of sections in arbitrary places [*]; > does the RiscV ABI ha...

By the way, since this is an optional code relaxation, we can think about it later. The first thing I would do is to add RISC-V support to lld without code shrinking relaxations, which I believe is doable by at most a few hundreds lines of code. On Wed, Jul 12, 2017 at 3:21 AM, Rui Ueyama <ruiu at google.com> wrote: > On Tue, Jul 11, 2017 a...

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructio...

...klibc/klibc.git;a=commit;h=83fcb05804497482caab9a77451907f1a5a6a8e2 Author: Ben Hutchings <ben at decadent.org.uk> AuthorDate: Sat, 29 Aug 2020 21:59:24 +0100 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Sun, 30 Aug 2020 00:48:29 +0100 [klibc] riscv64: Make linker relaxation work and enable it RISC-V code generally needs two instructions to address static data, but up to 4K of static data in an executable can be addressed using a single instruction. The linker "relaxes" a two-instruction sequence to one instruction, assuming that the gp register is initiali...

...ed by default at -O0, > run "clang -c test.c -v" and you will see -mrelax-all being passed, > but not if you add -O1. > > It is not used on optimized builds because it produces larger binaries. > Yep. So if we intend to keep it around I propose to rename it to -mc-optimize-relaxation, or -mc-fast-relaxation or something of the sort (I think that the flag is obscure enough to deserve a long, verbose and descriptive name). Eli

...relocations even if they are in the same section. I think > that means object files for RISC-V have many more relocations than the other > architectures. Is this correct? Indeed. RISC-V would need to emit relocations for PC-relative offsets otherwise those offsets will become incorrect after relaxation. On Wed, Jul 12, 2017 at 2:27 AM, Rui Ueyama via llvm-dev <llvm-dev at lists.llvm.org> wrote: > By the way, since this is an optional code relaxation, we can think about it > later. The first thing I would do is to add RISC-V support to lld without > code shrinking relaxations, whic...

>> It is not used on optimized builds because it produces larger binaries. >> > > Yep. So if we intend to keep it around I propose to rename it to > -mc-optimize-relaxation, or -mc-fast-relaxation or something of the > sort (I think that the flag is obscure enough to deserve a long, > verbose and descriptive name). So, normally "optimize" in a compiler means "produce better code", not "produce code faster", so -mc-optimize-relaxati...

...t the following error message: ldc2.exe: CommandLine Error: Option 'aarch64-branch-relax' registered more than once! LLVM ERROR: inconsistency in registered CommandLine options Reason is that the option 'aarch64-branch-relax' is registered in file lib/Target/AArch64/AArch64BranchRelaxation.cpp and a second time through PassRegistry::registerPass() (because of the use of the NameParser - the pass is also named 'aarch64-branch-relax'). Is this the intended behavior? If yes, what can I do to fix the compiler? Regards, Kai

...7 at 6:59 PM, Rafael Avila de Espindola < rafael.espindola at gmail.com> wrote: > Rui Ueyama via llvm-dev <llvm-dev at lists.llvm.org> writes: > > > tl;dr: TLSDESC have solved most problems in formerly inefficient TLS > access > > models, so I think we can drop TLS relaxation support from lld. > > > > lld's code to handle relocations is a mess; the code consists of a lot of > > cascading "if"s and needs a lot of prior knowledge to understand what it > is > > doing. Honestly it is head-scratching and needs serious refactoring. I...

...ytes > I've also did some testing with a worst case assembler file doing lots > of jumps that can all be relaxed. In that case, -mno-relax-all was 25%. > If the above observation can be confirmed, I believe there is no good > reason to keep -mrelax-all. To the best of my knowledge relaxation is more expensive on ELF than on Mach-O since there are less opportunities on Mach-O. Given that, I think it is save to conclude that we can drop relax-all (and that I should figure out what is going on with the size of debug binaries on ELF). > Joerg Cheers, Rafael

...klibc/klibc.git;a=commit;h=a966c3a12ee8b921dc669647c1fe75b25f72e604 Author: Ben Hutchings <ben at decadent.org.uk> AuthorDate: Sat, 29 Aug 2020 21:59:24 +0100 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Sat, 29 Aug 2020 23:33:09 +0100 [klibc] riscv64: Make linker relaxation work and enable it RISC-V code generally needs two instructions to address static data, but up to 4K of static data in an executable can be addressed using a single instruction. The linker "relaxes" a two-instruction sequence to one instruction, assuming that the gp register is initiali...

Hi All, I have a question about relaxation stuff in MC assembler. I am encoding conditional branch instructions with PC relative address in assembler. I have met some tests with relative offsets over the instruction's address field. I think I need to change the conditional instruction to multiple instructions with basic blocks for e...

On Tue, Nov 7, 2017 at 8:16 PM, Rafael Avila de Espindola < rafael.espindola at gmail.com> wrote: > Rui Ueyama <ruiu at google.com> writes: > > >> So I am strongly against removing either non TLSDESC support of support > >> for the relaxations. > >> > > > > It's still pretty arguable. By default, compilers use General Dynamic > model > > with -fpic, and Initial Exec without -fpic. > > It is more complicated than that. You can get all 4 modes with clang > > ------------------------------- &gt...

tl;dr: TLSDESC have solved most problems in formerly inefficient TLS access models, so I think we can drop TLS relaxation support from lld. lld's code to handle relocations is a mess; the code consists of a lot of cascading "if"s and needs a lot of prior knowledge to understand what it is doing. Honestly it is head-scratching and needs serious refactoring. I'm trying to simplify it to make it manage...