Displaying 5 results from an estimated 5 matches for "relationmap".
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relational
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
...erested in mapping relations, need to
define a
// class of its own as a subclass of 'Relations'.
class IFormat<bits<4> value> { // Used to define basic instruction formats,
Ex: register-register, register-immediate
bits<4> Value = value;
}
// class RelationMap is actually used to related instructions with each
other.
class RelationMap<IFormat pFormat, IFormat iFormat, list<string> ancestors =
[] > {
IFormat ParentFormat = pFormat;
IFormat InstrFormat = iFormat;
list <string> Ancestors = ancestors;
}
2) Include some basic setup i...
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
>
> Currently, we rely on switch tables to transform between formats. However,
> we would like to have a different mechanism to represent these relationships
> instead of switch tables. I am thinking of modeling these relations in
> HexagonInstrInfo.td file and use TableGen to generate a table with
2012 Aug 01
3
[LLVMdev] TableGen related question for the Hexagon backend
Hi,
I'm looking for some suggestions on a problem related to the Hexagon
backend.
Hexagon architecture allows instructions in various formats. For example, we
have 3 variations of the add instruction as defined below:
ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 =
add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is
true ADDrr_np :
2012 Aug 17
0
[LLVMdev] TableGen related question for the Hexagon backend
...y , PredSense=true, PredSense=false
{ ADD , ADDtrue, ADDfalse, // BaseOpcode="ADD"
{ SUB , SUBtrue, SUBfalse, // BaseOpcode="SUB"
…
> 5) We need some changes in the TGParser.cpp so that it can use the
> information specified
> through the RelationMap and populate relevant fields in the RelHexagon
> class.
The tablegen parser is definitely not the right place to implement this.
/jakob
2012 Aug 17
2
[LLVMdev] TableGen related question for the Hexagon backend
...PredSense=false
> { ADD , ADDtrue, ADDfalse, // BaseOpcode="ADD"
> { SUB , SUBtrue, SUBfalse, // BaseOpcode="SUB"
>
> > 5) We need some changes in the TGParser.cpp so that it can use the
> > information specified through the RelationMap and populate relevant
> > fields in the RelHexagon class.
>
> The tablegen parser is definitely not the right place to implement this.
I didn't want to modify the tablegen parser either. But, I couldn't think of
a way around it. Once instructions are expended by the TableGen p...