Displaying 2 results from an estimated 2 matches for "regvec0".
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degvec
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...4 [ %index.next, %vector.body ], [ 0, %vector.body.preheader ]
%vec.phi = phi <8 x i64> [ %0, %vector.body ], [ zeroinitializer,
%vector.body.preheader ]
The ASM code generated from it is the following:
LBB0_3: // %vector.body.preheader
REGVEC0 = 0
mov r0, 0
std -48(r10), r0
std -128(r10), REGVEC0
jmp LBB0_4
LBB0_4: // %vector.body
ldd REGVEC0, -128(r10)
ldd r0, -48(r10)
I am surprised that the BPF scalar instructions ldd an...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...0,
> %vector.body.preheader ]
> %vec.phi = phi <8 x i64> [ %0, %vector.body ], [ zeroinitializer,
> %vector.body.preheader ]
>
> The ASM code generated from it is the following:
> LBB0_3: // %vector.body.preheader
> REGVEC0 = 0
> mov r0, 0
> std -48(r10), r0
> std -128(r10), REGVEC0
> jmp LBB0_4
> LBB0_4: // %vector.body
> ldd REGVEC0, -128(r10)
> ldd r0, -48(r10)
>
> I am surp...