search for: reguse

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2013 Oct 22
1
[LLVMdev] System call miscompilation using the fast register allocator
...and it appears all is well after 'Two-Address instruction pass': MOV32mi <fi#0>, 1, %noreg, 0, %noreg, 1; mem:ST4[%val] %vreg3<def> = MOV64ri64i32 4; GR64:%vreg3 %R8<def> = COPY %vreg3; GR64:%vreg3 INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R8 %vreg4<def> = LEA64r <fi#0>, 1, %noreg, 0, %noreg; GR64:%vreg4 %R10<def> = COPY %vreg4; GR64:%vreg4 INLINEASM <es:> [sideeffect] [attdialect], $0:[reguse], %R10 %vreg5<def> = MOV64ri64i32 3; GR64:%vreg5 %RDX<def> = COPY %vreg5; GR64...
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...… BB#21: derived from LLVM BB %if.end Live Ins: %LR %R2 %R3 %R4 %R5 %R7 %R12 Predecessors according to CFG: BB#6 BB#20 BB#9 BB#14 INLINEASM <es:ldaexd $0, ${0:H}, [$1];> [sideeffect] [mayload] [maystore] [attdialect], $0:[regdef-ec:GPRPair], %R8_R9<earlyclobber,def>, $1:[reguse:GPR], %R4, <!3> %R0<def> = ANDri %R7, 1, pred:14, pred:%noreg, opt:%CPSR<def> %R0<def> = MOVr %LR, pred:1, pred:%CPSR<kill>, opt:%noreg %R1<def> = EORrr %R0, %LR, pred:14, pred:%noreg, opt:%noreg %R1<def> = ANDrr %R9, %R1<...
2011 Sep 26
1
[LLVMdev] distinguishing between real arguments and variable arguments
...erands that we care about during hazard detection. case MBlaze::BRLID: case MBlaze::BRALID: case MBlaze::BRLD: case MBlaze::BRALD: return 2; } } In Sparc: void Filler::insertCallUses(MachineBasicBlock::iterator MI, SmallSet<unsigned, 32>& RegUses) { switch(MI->getOpcode()) { default: llvm_unreachable("Unknown opcode."); case SP::CALL: break; case SP::JMPLrr: case SP::JMPLri: assert(MI->getNumOperands() >= 2); const MachineOperand &Reg = MI->getOperand(0); assert(Reg.isReg() &&amp...
2007 Aug 10
1
[LLVMdev] inline assembly
...eems that there is no difference between input and output operands for memory constraints. can somebody confirm this? i could not find documentation on these flags, following the AddInlineAsmOperands it seems to be something like: 'Code | (Size << 3)' with Code on of these values: 1 REGUSE 2 REGDEF 3 IMM 4 MEM/ADDR are there any other values? and would it be safe to change 4 to MEMUSE and add 5 (MEMDEF)? i do not know where these values are used (except for the ISelDAG and the AsmPrinter). florian
2002 Oct 04
0
ITIL in Major Corporations - Has it worked? BREAKFAST SEMINAR - Tue 22/10/02
ITIL in Major Corporations - Has it worked? Speaker: Gerard Blokdijk, Managing Director The Art of Service When: Tuesday 22 October - 7.30am to 9.30am Venue: Regus Citigroup Centre, 2 Park Street, Sydney Cost: $45 including GST Features: Breakfast, Networking. Already over 30 participants - CIO's / (IT) Managers. Register: http://www.artofservicedirect.com click on Enrol, Sydney Events ALSO:
2013 Jan 08
2
[LLVMdev] Inline asm bug?
...RDI %vreg0<def> = COPY %RDI; GR64:%vreg0 MOV32mi %RIP, 1, %noreg, <ga:@G>, %noreg, 0; mem:ST4[@G](tbaa=!"int") %vreg2<def> = COPY %vreg0; GR64:%vreg2,%vreg0 INLINEASM <es:> [attdialect], $0:[regdef:GR32], %vreg1<def>, $1:[reguse:GR64], %vreg2, $2:[clobber], %EFLAGS<earlyclobber,imp-def>, <<badref>>; GR32:%vreg1 GR64:%vreg2 %EAX<def> = COPY %vreg1; GR32:%vreg1 RET # End machine code for function foo. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora F...
2020 Feb 22
2
COPYs between register classes
Hi, On SystemZ there are a set of "access registers" that can be copied in and out of 32-bit GPRs with special instructions. These instructions can only perform the copy using low 32-bit parts of the 64-bit GPRs. As reported and discussed at https://bugs.llvm.org/show_bug.cgi?id=44254, this is currently broken due to the fact that the default register class for 32-bit integers is