search for: regstospil

...gt; StackInt = &LSS.getInterval(StackSlot); > > if (Original != Edit->getReg()) > VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); > > assert(StackInt->getNumValNums() == 1 && "Bad stack interval values"); > for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) > StackInt->MergeSegmentsInAsValue(LIS.getInterval(RegsToSpill[i]), > StackInt->getValNumInfo(0)); > DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n'); > > And this...

Hi, Can anyone help me with the stack slot coloring optimization? This corresponding file is /lib/codegen/stackslotcoloring.cpp. It is said this optimization was for stack slot overlay for frame size reduction, after register allocation phase. And this transformation pass relies on the LiveStack analysis pass. How, when checking the source code, it seems the LiveStack analysis has not been

Hi Quentin, On 08/19/14 18:58, Quentin Colombet wrote: [...] > It seems that you will have to debug further the *** Bad machine code: Instruction loads from dead spill slot *** before we can be of any help. Yes, I've done some more digging. Sorry for the long mail... I get: Inline spilling aN40_0_7:%vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r At this point I have