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...clobbered. I don't know about you, but it was hard for me to read the source and understand what was going on without looking at the header file. So, I made these changes. Instead of all of the booleans, you pass in a flag that has bits set to indicate what state the register is in: namespace RegState { enum { Define = 0x1, Implicit = 0x2, Kill = 0x4, Dead = 0x8, EarlyClobber = 0x10, ImplicitDefine = Implicit | Define, ImplicitKill = Implicit | Kill }; } class MachineInstrBuilder { MachineInstr *MI; public: explicit Mach...

...a LDRD instruction. Ops.pop_back(); Ops.pop_back(); // Form the pair instruction. if (isLd) { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc)) .addReg(EvenReg, RegState::Define) .addReg(OddReg, RegState::Define) .addReg(BaseReg); if (!isT2) MIB.addReg(OffReg); MIB.addImm(Offset).addImm(Pred).addReg(PredReg); ++NumLDRDFormed; On Tue, Sep 7, 2010 at 1:31 PM, Bill Wendling <wendling a...

On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote: > I have two questions regarding MachineMemOperands and dependence information. > > Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. > > (before optimization) > %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;

...amp;& "Invalid Pointer Size!"); + + unsigned Buf = MI->getOperand(0).getReg(); + unsigned JmpLoc = MRI.createVirtualRegister(&SP::IntRegsRegClass); + + // Instruction to load jmp location + MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri)) + .addReg(JmpLoc, RegState::Define) + .addReg(Buf) + .addImm(PtrSize); + MIB.setMemRefs(MMOBegin, MMOEnd); + + // TO DO: If we do 64-bit handling, this perhaps should be FLUSHW, not TA 3 + const long int TRAP_COND_ALWAYS = 0x08; + MIB = BuildMI(*MBB, MI, DL, TII->get(SP::TRAPri), SP::G0).a...

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,

...nstant values and virtual registers. What I really want to achieve is a push-pop of a register to have a temporary to work with, without having to check if this register is defined or not. However, whenever the reg is not defined before the push, the MachineVerifier complains about that. If I add RegState::Undef to the push, the verifier complaint goes away, but I worry that this might be unsafe. I would like "Undef" for physical registers to mean "we don't care if this register has been defined or not", but perhaps it means "this register can now have any bits set&quot...

...lass within reason, +            // just like what AddRegisterOperand will allow. +            const TargetRegisterClass *ConstrainedRC +              = MRI->constrainRegClass(Reg, RC, MinRCSize); +            if (ConstrainedRC) {                VRBase = Reg;                MIB.addReg(VRBase, RegState::Define);                break;              }            }          }        } Why do the register classes currently have to match exactly in this case? It seems that these COPYs that now remain may end up in the same register class, if the users require it. So why not constrain also here...

On 13/05/2009, at 02.46, Bill Wendling wrote: > Instead of all of the booleans, you pass in a flag that has bits set > to indicate what state the register is in: > > namespace RegState { > enum { > Define = 0x1, > Implicit = 0x2, > Kill = 0x4, > Dead = 0x8, > EarlyClobber = 0x10, > ImplicitDefine = Implicit | Define, > ImplicitKill = Implicit | Kill > }; > } [...] > MachineInstrBuilder...

...Dunno why it doesn't. Once you move beyond the fixed operands, it can't be determined automatically if the added register should be a use or a def. But I think it would be convenient to add addUse() and addDef() methods to MachineInstrBuilder, instead of requiring the tedious addReg(..., RegState::Define). /jakob

...."); + + // Make sure that R4 may be used as scratch. Add an additional tPUSH (R4) + // if necessary. + if (!IsR4IncludedInCSI) { + IsR4ToBeAdditionallyAddedToPopIns = true; + + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPUSH)) + .addReg(ARM::R4,RegState::Kill)); + + StackSlotForSavedLR ++; + } + + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi)) + .addReg(ARM::R4, RegState::Define) + .addReg(ARM::SP) + .addImm(StackSlotForSavedLR)); + + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr...

...{ StackProbeSymbol = "__chkstk"; - isSPUpdateNeeded = true; } } else if (STI.isTargetCygMing()) StackProbeSymbol = "_alloca"; @@ -657,15 +655,15 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit) .setMIFlag(MachineInstr::FrameSetup); - // MSVC x64's __chkstk does not adjust %rsp itself. - // It also does not clobber %rax so we can reuse it when adjusting %rsp. - if (isSPUpdateNeeded) { + if (Is64Bit) { + // MSVC x64's __chkstk...

Hello everyone, I'm a newbie of llvm. I'm trying to insert Intel MPX instruction BNDCU with BuildMI. I add my machinefunctionpass at addPreEmitPass2. Here is the code of insertion: BuildMI(MBB, MI, DL, TII->get(X86::BNDCU64rr)).addReg(X86::BND2, RegState::Define).addReg(X86::R10); And here is to stack track when I compiler program with modified llc: /home/shenyouren/workspace/build-llvm/bin/llc -o obj/simple.s obj/simple-opt.bc llc: /home/shenyouren/workspace/llvm/include/llvm/ADT/SmallVector.h:154: const T& llvm::SmallVectorTemplateCommon&l...

...de::COPY), - regA).addReg(regB); + unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); + if (regASubIdx) { + BuildMI(*mbbi, mi, mi->getDebugLoc(), + TII->get(TargetOpcode::COPY)). + addReg(regA, RegState::Define, regASubIdx).addReg(regB); + } + else { + BuildMI(*mbbi, mi, mi->getDebugLoc(), + TII->get(TargetOpcode::COPY), regA).addReg(regB); + } } MachineBasicBlock::iterator prevMI = prior(mi);...

I'm not sure. It certainly seems reasonable to me that the building could/should set default Define flags on operands based on the MCInstrDesc. Dunno why it doesn't. -Jim On Feb 19, 2013, at 7:14 PM, reed kotler <rkotler at mips.com> wrote: > Hi Jim, > > One thing that seems strange to me is that if do a BuildMI, if you put a register inside the first parens, then it

...he operands (does it currently?). Right now it's pretty easy to construct an MI that's inconsistent with its MCInstrDesc information. -Jim > > But I think it would be convenient to add addUse() and addDef() methods to MachineInstrBuilder, instead of requiring the tedious addReg(..., RegState::Define). > > /jakob >

Hi Jim, One thing that seems strange to me is that if do a BuildMI, if you put a register inside the first parens, then it will treat it as a def, but if you just .addReg it won't (by default), even though it should know from the instruction definition. Seems like it should do that. Why would you want it to not do that? Reed On 02/18/2013 01:22 PM, Jim Grosbach wrote: > Hi Reed,

Mingw switched abis with the release of gcc 4.7 (http://gcc.gnu.org/gcc-4.7/changes.html). The main change is that now mingw (like msvc) given thiscall calling convention to methods by default. I think the last bug blocking us to support the new abi has just been fixed. The question now is how to switch. The attached patches simply switch llvm and clang to the new ABI. This is similar to what

Hi, I'm having some trouble wirting an instruction in the X86 backend. I made a new intrinsic and I wrote a custom inserter for my intrinsic in the X86 backend. Everything works fine, except for one instruction that I can't find how to write. I want to add this instruction in one of my machine basic block: mov [rdi], 0 How can I achieve that with the LLVM api? I tried several