search for: regsiters

...he ultimate "one handset" solution is getting closer. If Wi-Fi weren't so rubbish and my house not made of Dartmoor Granite it might have half a chance of working outside the room with the access point, however ... Anyone tried the Plantronics Voyager 510 bluetooth headsets which regsiters to both a mobile phone and their own base unit (which presumably has a USB sound device) as in: https://www.ukheadsets.co.uk/thc-plantronics-voyager-510-usb-dongle-rn-422-action-show_detail-show_products_mode-cat_click I'm not a fan of soft-phones, and not sure I want to have a borg implant...

I have noticed a strange behaviour when our internet connection was down a couple of hours last week. What happens is that asterisk starts running *really* slow. If I type "sip show peers" it sometimes responds correctly and shows all the connected peers, but sometimes I get an empty list (this seems to go in cycles). Also the connected polycom phones seems to be unable to place any

Hello Matthias, On 28 July 2017 at 04:13, Matthias Braun <mbraun at apple.com> wrote: > It's not that hard in principle: > - A register class is a set of registers. > - Virtual Registers have a register class assigned. > - If you have register constraints (like x86 8bit operations only work on > al,ah,etc.) then you have to create a new register class to express that.

...VM front end, but I am > not very sure if at the time that the llvm_c_expand_body_1 function is called, the SSA form was > already constructed (each definition dominates all the uses). Can somebody please tell me? The LLVM GCC frontend does not translate variables directly into LLVM virtual regsiters (which must be in SSA form). Instead, the LLVM GCC frontend simply uses a memory location for each variable (e.g. a local variable is allocated via the LLVM alloca instruction). If you use llvm-gcc -S -o file.ll file.c, you can see the code that llvm-gcc generates. Next, gccas (after assembli...

Hi, I have been looking into the code that generates the LLVM assembly in the LLVM front end, but I am not very sure if at the time that the llvm_c_expand_body_1 function is called, the SSA form was already constructed (each definition dominates all the uses). Can somebody please tell me? Thanks

Hello everyone, I noticed that there are several register classes defined in X86 target and many of them are overlapping. Is there a list of all X86 register classes documented somewhere? I found many listed in X86GenRegisterInfo.inc(generated by tablegen) but unsure if that is the complete list. Also, is there documentation on the role and purpose of these classes and how the X86 backend decides

...t; not very sure if at the time that the llvm_c_expand_body_1 function is called, the SSA form > was > > already constructed (each definition dominates all the uses). Can somebody please tell me? > > The LLVM GCC frontend does not translate variables directly into LLVM > virtual regsiters (which must be in SSA form). > > Instead, the LLVM GCC frontend simply uses a memory location for each > variable (e.g. a local variable is allocated via the LLVM alloca > instruction). If you use llvm-gcc -S -o file.ll file.c, you can see the > code that llvm-gcc generates. &gt...

...ptimized, but reserved registers are implicitly live out of the frame. Reserved register writes should not move across calls. See http://reviews.llvm.org/D15667. Indeed the current code respects ordering dependencies for reserved registers, so rule 3) above can just be removed and we treat reserved regsiters like any other for reordering. We can handle them like any other register for calls as well then I guess? Moving through calls should be legal if the calls regmask shows they are preserved, or do you have an example where this would be bad? - Matthias > >> == Motivation == >> Gene...

Hi Daniel, On 13.09.2018. 19:32, Daniel Sanders wrote: > Could you clarify what you mean here? The new legalizer info can > define this with: >     getActionDefinitionsBuilder(G_SELECT).clampScalar(1, s32, s32) > so I'm guessing you mean that code to mutate the G_SELECT is currently > missing Yes, LegalizerHelper::widenScalar widens only TypeIdx==0, it doesn't do that

...or allocate/get new virtual > register. Okay, the problem with this is that the instruction selector is the code that is supposed to know what constraints the instructions have. For example, on many architectures, immediates are limited to 13 bits or some other small number. Also, for virtual regsiters, there is no context to hold the mapping of Value*'s -> vregs: this is what the instruction selector is about. I recommend taking a look at the getReg(*) methods in the X86 instruction selector. The basic code generation stage for an add, boiled down to its simplest form, basically looks l...

Note: Question is written after describing what I have coded. Hello LLVMDevs, I am trying to impliment floating point comparsion for an architecture which supports following type of floating point comparision if FPU is available: fcmp.un --> true if one of the operand is NaN fcmp.lt --> ordered less than, if any input NaN then return false fcmp.eq --> ordered equal, if any input NaN

Hi All, AVX-512 introduced the K mask registers and masked operations which make a natural choice for legalizing vectors of i1's. For example, define <8 x i32> @foo(<8 x i32>%a, <8 x i32*> %p) { %r = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %p, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>,

Hi, We are working on a research project whose objective is developing a pre-allocation scheduling algorithm that achieves the optimal balance between exploiting ILP (hiding latencies) and minimizing register pressure.  A prototype of our algorithm has been implemented and integrated into an experimental version of LLVM 2.9. Our algorithm is based on a combinatorial optimization approach, which

Ok, I'm now trying to write instruction selector and have some questions 1. The MachineInstrBuilder has methods to add register operand and immediate operand. However, what would be really nice is a method to add Value*. So, I would write: BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); and depending on whether the passed Value* is contant or instruction, the add

Any one know of software that allows 2-way radios as VoIP(SIP) clients, besides dingotel's usb & mic cable trick ? http://www.dingotel.com/2way/requirements2way.asp They might be ok if the SIP client was not hardcode to their own SIP proxy Has anyone tried any hacks to get the 2-way radio SIP client to regsiter to a * box. hmm chan_frsgmfrs anyone? using the usb/mic cable under linux :)

On Thu, Mar 9, 2017 at 9:35 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 02/25/2017 03:06 AM, vivek pandya via llvm-dev wrote: > > Note: Question is written after describing what I have coded. > > Hello LLVMDevs, > > I am trying to impliment floating point comparsion for an architecture > which > supports following type of floating point comparision if FPU

On Feb 12, 2009, at 1:41 AM, [Alex] wrote: > They "should" be non-allocatable if the hardware implements the same > number > of these i32 registers as the "specification". The input language > (which is > converted to LLVM IR) may use up to 4 registers but the hardware > only has 2. > So they must be allocatable, right? To be allocatable, the code

Chris Lattner-2 wrote: > > and out of the registers and must be able to spill them, even if it > means going through another temporary register class. > But what if it cannot even be copied to another temporary register class? The values of these i32 regsiters can only be used as the index of another register class, but the value of the index itself cannot be read. Usually the program can be generated using only 2 of these i32 index registers, but the problem is LLVM requires them to be copyable if there is a PHI node. -- View this message in context:...

On Wed, 2010-04-14 at 17:30 -0700, Hisham Chowdhury wrote: > > > > - Is there a utility to clone a MachineBasicBlock in LLVM > > > > > > There is CloneBasicBlock routine in ./lib/Transforms/Utils/CloneFunction.cpp - Sanjiv > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu

Hello , I have written a very simple MachineFunction Pass that currently does nothing. It compiles fine but when I try to load it with llc it give me following error: llc -optimize-regalloc=0 -load lib/GCRA.dylib -regalloc=gc test/fibo.bc Pass 'Bundle Machine CFG Edges' is not initialized. Verify if there is a pass dependency cycle. What is going wrong here ? Here is my very simple