search for: regsit

...he ultimate "one handset" solution is getting closer. If Wi-Fi weren't so rubbish and my house not made of Dartmoor Granite it might have half a chance of working outside the room with the access point, however ... Anyone tried the Plantronics Voyager 510 bluetooth headsets which regsiters to both a mobile phone and their own base unit (which presumably has a USB sound device) as in: https://www.ukheadsets.co.uk/thc-plantronics-voyager-510-usb-dongle-rn-422-action-show_detail-show_products_mode-cat_click I'm not a fan of soft-phones, and not sure I want to have a borg impl...

...calls into asterisk in the same cycles. The phone tries to initiate a connection to astersk, but gets no response at all. Other sympthoms are that if I restart asterisk it takes *very* long time for it to start. (we are talking minutes). It seems the situation is improved when I remove the "regsiter => " statements in my sip.conf. I have tried doing a tcpdump to figure our what is going on but I can see no packets going in our out during the "stalled" periods. I am running bristuffed 1.0.6. Our setup is one external ISDN + a couple of external SIP connections. Internal IS...

...like x86 8bit operations only work on > al,ah,etc.) then you have to create a new register class to express that. > (The only exception being limited to a single register, which instead we > express by assigning the physreg directly instead of using a vreg). > - Tablegen may create more regsiter classes for register coalescing where > we want to accomodate constraints of multiple instructions at the same time. > - All the information is in the .td file; you just have to put some effort > into learning tablegen as the information is often expressed by using > functions (i.e. t...

...VM front end, but I am > not very sure if at the time that the llvm_c_expand_body_1 function is called, the SSA form was > already constructed (each definition dominates all the uses). Can somebody please tell me? The LLVM GCC frontend does not translate variables directly into LLVM virtual regsiters (which must be in SSA form). Instead, the LLVM GCC frontend simply uses a memory location for each variable (e.g. a local variable is allocated via the LLVM alloca instruction). If you use llvm-gcc -S -o file.ll file.c, you can see the code that llvm-gcc generates. Next, gccas (after assem...

Hi, I have been looking into the code that generates the LLVM assembly in the LLVM front end, but I am not very sure if at the time that the llvm_c_expand_body_1 function is called, the SSA form was already constructed (each definition dominates all the uses). Can somebody please tell me? Thanks

Hello everyone, I noticed that there are several register classes defined in X86 target and many of them are overlapping. Is there a list of all X86 register classes documented somewhere? I found many listed in X86GenRegisterInfo.inc(generated by tablegen) but unsure if that is the complete list. Also, is there documentation on the role and purpose of these classes and how the X86 backend decides

...t; not very sure if at the time that the llvm_c_expand_body_1 function is called, the SSA form > was > > already constructed (each definition dominates all the uses). Can somebody please tell me? > > The LLVM GCC frontend does not translate variables directly into LLVM > virtual regsiters (which must be in SSA form). > > Instead, the LLVM GCC frontend simply uses a memory location for each > variable (e.g. a local variable is allocated via the LLVM alloca > instruction). If you use llvm-gcc -S -o file.ll file.c, you can see the > code that llvm-gcc generates....

...ptimized, but reserved registers are implicitly live out of the frame. Reserved register writes should not move across calls. See http://reviews.llvm.org/D15667. Indeed the current code respects ordering dependencies for reserved registers, so rule 3) above can just be removed and we treat reserved regsiters like any other for reordering. We can handle them like any other register for calls as well then I guess? Moving through calls should be legal if the calls regmask shows they are preserved, or do you have an example where this would be bad? - Matthias > >> == Motivation == >> G...

...)       .legalFor({{s32, s1}, {s64, s1}, {p0, s1}})       .clampScalar(0, s32, s64)       .widenScalarToNextPow2(0); In this case LLT of operand 1 (s1) in G_SELECT has size 1, and corresponding register class in selected instruction has size 32 (that is $src1 in AArch64::ANDSWri, it has GPR32 regsiter class). For that reason s1 is practically ignored and silently converted to s32. We could get similar result if we have:   getActionDefinitionsBuilder(G_SELECT)       .legalFor({{s32, s32}, {s64, s32}, {p0, s32}})       .clampScalar(0, s32, s64)       .clampScalar(1, s32, s32)       .widenS...

...or allocate/get new virtual > register. Okay, the problem with this is that the instruction selector is the code that is supposed to know what constraints the instructions have. For example, on many architectures, immediates are limited to 13 bits or some other small number. Also, for virtual regsiters, there is no context to hold the mapping of Value*'s -> vregs: this is what the instruction selector is about. I recommend taking a look at the getReg(*) methods in the X86 instruction selector. The basic code generation stage for an add, boiled down to its simplest form, basically look...

...ak; } } I am generating wrong code when using floating point library call for comparions. For the following simple case: float branchTest(float a, float b) { float retVal; if (a == b) { retVal = a / b + 22.34; } return retVal; } I am getting: brlid r15,__nesf2 nop beqi r3,.LBB0_2 ; r3 is return regsiter Now I want to understand difference between three different version of Condition Codes for same operation and how according to my target I should handle them. For example let's consider SETNE, SETONE and SETUNE so for my architecture I think for floating point all three are same so do I need...

...ing. As a side-note, with GlobalISel this can be solved, since we see the entire use-def chain at the function level. Our initial thought was to write a pass that will be run after ISel to correct bad selections. The pass would examine the use-def chains containing values that were selected to K-regsiter classes, and, when profitable, re-assign the values to GPR register classes (and replace the producing/consuming instructions accordingly). But even with this fix-up pass, we would still be losing many ISel pattern-matching rules that will be missed because the instruction set acting on GPR is ri...

...k? (2) Can we safely assume that CopyFromReg instrs and CopyToReg instrs are used for the sole purpose of representing live-in and live-our regs? In other words, are there other uses for these? If yes, how do we identify the ones that represent live-in and live-out regs. (3) The current physical regsiter limits obtained using TargetRegisterInfo::getRegPressureLimit() seem to be too low (for example, 3 integer regs on x86 32-bit mode). Are these good limits to use in our case? If not, how can we get better limits? Thank you in advance! -Ghassan -------------- next part -------------- An HTML at...

Ok, I'm now trying to write instruction selector and have some questions 1. The MachineInstrBuilder has methods to add register operand and immediate operand. However, what would be really nice is a method to add Value*. So, I would write: BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); and depending on whether the passed Value* is contant or instruction, the add

...of software that allows 2-way radios as VoIP(SIP) clients, besides dingotel's usb & mic cable trick ? http://www.dingotel.com/2way/requirements2way.asp They might be ok if the SIP client was not hardcode to their own SIP proxy Has anyone tried any hacks to get the 2-way radio SIP client to regsiter to a * box. hmm chan_frsgmfrs anyone? using the usb/mic cable under linux :)

...oint library call for > comparions. For the following simple case: > float branchTest(float a, float b) { > float retVal; > if (a == b) { > retVal = a / b + 22.34; > } > return retVal; > } > I am getting: > brlid r15,__nesf2 > nop > beqi r3,.LBB0_2 ; r3 is return regsiter > > Now I want to understand difference between three different version of > Condition > Codes for same operation and how according to my target I should handle > them. > For example let's consider SETNE, SETONE and SETUNE so for my architecture > I think for floating poi...

On Feb 12, 2009, at 1:41 AM, [Alex] wrote: > They "should" be non-allocatable if the hardware implements the same > number > of these i32 registers as the "specification". The input language > (which is > converted to LLVM IR) may use up to 4 registers but the hardware > only has 2. > So they must be allocatable, right? To be allocatable, the code

Chris Lattner-2 wrote: > > and out of the registers and must be able to spill them, even if it > means going through another temporary register class. > But what if it cannot even be copied to another temporary register class? The values of these i32 regsiters can only be used as the index of another register class, but the value of the index itself cannot be read. Usually the program can be generated using only 2 of these i32 index registers, but the problem is LLVM requires them to be copyable if there is a PHI node. -- View this message in conte...

On Wed, 2010-04-14 at 17:30 -0700, Hisham Chowdhury wrote: > > > > - Is there a utility to clone a MachineBasicBlock in LLVM > > > > > > There is CloneBasicBlock routine in ./lib/Transforms/Utils/CloneFunction.cpp - Sanjiv > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu

...oad it with llc it give me following error: llc -optimize-regalloc=0 -load lib/GCRA.dylib -regalloc=gc test/fibo.bc Pass 'Bundle Machine CFG Edges' is not initialized. Verify if there is a pass dependency cycle. What is going wrong here ? Here is my very simple code: //===-- GCRA.cpp - Regsiter Allocator --------------------------------===// // // // //===-----------------------------------------------------------------===// // // This is very simple register allocator based on George and Appel. // //===-----------------------------------------------------------------===// #include &qu...