search for: regpair

...ust follow any register-pairing rule defined for any such occurence. Possibly, one could add a Constraint per instruction def as well to indicate the use of the register pairing rule, and to allow instances where it does not apply. PBQP extension (suggestion) ====================== Tablegen: def regPair : registerPair<AddrReg0, OffsReg0>, ~or~ def regPair: registerPairing<AddrReg0, [OffsReg0, OffsReg1, OffsReg2]>; ~or~ ?? in the instruction such as a load: ld dst, addrReg, offsReg then PBQP must follow the rule and only allocate legal combinations of addrReg and offsReg. I beleive...

...ify complicated constraints that the normal constraint model doesn't support. Constraints are modeled as matrices, so any specific type of constraint wouldn't be mentioned in the source file. > PBQP extension (suggestion) > ====================== > > Tablegen: > > def regPair : registerPair<AddrReg0, OffsReg0>, > ~or~ > def regPair: registerPairing<AddrReg0, [OffsReg0, OffsReg1, OffsReg2]>; > ~or~ > ?? I am not sure how much easier that would be than the current approach. I'll leave that up to Lang. > I beleive this should work by setti...

On Jan 19, 2012, at 5:31 AM, Jonas Paulsson wrote: > LLVM would have to be extended with an RegClass/register-attribute 'spillable' What exactly are you proposing? Why can't you do what the PowerPC and Hexagon targets do? Spill-free register allocation sounds great, why not do it for all register classes? > , and a register allocator would have to implement register pairing.

...to make the PEI pass save/restore only one half of a register pair if the other half is not being used, instead of saving the whole pair. Here is an example of what I try to explain to make things more clear: Suppose this situation where we have a register file of 8bit regs, and that you can form regpairs by joining two adjacent regs. Pairs are pseudo regs that are formed by two 8 bit subregisters, with their lo and hi parts defined in the register.td file. Both 8 and 16bit types are legal. In the following function: char foo(char a, char b, char c, int d) Arguments are passed this way: a=R10, b=R8...

...he PEI pass save/restore only one half of a register pair if the other half is not being used, instead of saving the whole pair. Here is an example of what I try to explain to make things more clear: > > Suppose this situation where we have a register file of 8bit regs, and that you can form regpairs by joining two adjacent regs. Pairs are pseudo regs that are formed by two 8 bit subregisters, with their lo and hi parts defined in the register.td file. Both 8 and 16bit types are legal. > In the following function: char foo(char a, char b, char c, int d) > Arguments are passed this way: a...

Hi, My target has special requirements during register allocation - there is both a need to handle register pairing and to never spill a flag result reg-class (which might happen at -O0 for no obvious reason). Since neither of these issues seems to be supported, I have tried to pre-allocate these registers in the preRA pass. This has resulted in "using undefined physical register"

...ee it. it comes up in NetworkManager but never gets an IP. the router is a linksys using WPA/PSK security. Would/could someone please help me out trying to get this to work? Output of several commands follows: dmesg: ath: EEPROM regdomain: 0x69 ath: EEPROM indicates we should expect a direct regpair map ath: Country alpha2 being used: 00 ath: Regpair used: 0x69 phy0: Selected rate control algorithm 'ath9k_rate_control' Registered led device: ath9k-phy0::radio Registered led device: ath9k-phy0::assoc Registered led device: ath9k-phy0::tx Registered led device: ath9k-phy0::rx phy0: Ather...

Does LLVM support register aliases between classes that are not in a sub/super class relationship? Cameron

On Thu, Oct 27, 2011 at 9:29 AM, Johannes Birgmeier <e0902998 at student.tuwien.ac.at> wrote: > >> Hi Johannes, what processor are you targeting?  Is it little-endian or >> big-endian? > Little-endian. (The truth: you can set it manually, but it is set to > little endian, for sure.) The processor is a TI TMS320C64x. > > Follow-up: I discovered that the

...o lddw: Just print out stdw with the given pointer and the register pair, just like lddw. (This seems obvious.) Well, ****. I just read the documentation very carefully (yeah I know. I'm sorry) and it seems that stdw doesn't care about the big/little endian setting, it always writes the regpair into memory in big endian. lddw, however, DOES care about the setting - if little endian is enabled, the result register pair gets switched. What kind of confusion could have provoked the TI engineers to create such a horrible instruction set? OK, thanks for the hints. I'll try to sort thi...

> Hi Johannes, what processor are you targeting? Is it little-endian or > big-endian? Little-endian. (The truth: you can set it manually, but it is set to little endian, for sure.) The processor is a TI TMS320C64x. Follow-up: I discovered that the "guilty" method is DAGCombiner::ReduceLoadWidth. The error is introduced because the offset is not calculated correctly. The first

...dhci: Copyright(c) Pierre Ossman sdhci-pci 0000:02:00.1: SDHCI controller found [14e4:16bc] (rev 10) mmc0: SDHCI controller on PCI [0000:02:00.1] using ADMA Linux video capture interface: v2.00 ath: phy0: ASPM enabled: 0x42 ath: EEPROM regdomain: 0x6a ath: EEPROM indicates we should expect a direct regpair map ath: Country alpha2 being used: 00 ath: Regpair used: 0x6a ieee80211 phy0: Selected rate control algorithm 'minstrel_ht' ieee80211 phy0: Atheros AR9462 Rev:2 mem=0xffffc90025080000, irq=17 uvcvideo: Found UVC 1.00 device 1.3M HD WebCam (04f2:b2dc) input: 1.3M HD WebCam as /devices/pci00...

...none) kernel: ath9k 0000:01:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 Oct 8 02:35:04 (none) kernel: ath9k 0000:01:00.0: setting latency timer to 64 Oct 8 02:35:04 (none) kernel: ath: EEPROM regdomain: 0x60 Oct 8 02:35:04 (none) kernel: ath: EEPROM indicates we should expect a direct regpair map Oct 8 02:35:04 (none) kernel: ath: Country alpha2 being used: 00 Oct 8 02:35:04 (none) kernel: ath: Regpair used: 0x60 Oct 8 02:35:04 (none) kernel: phy0: Selected rate control algorithm ''ath9k_rate_control'' Oct 8 02:35:04 (none) kernel: Registered led device: ath9k-phy0::...

...6.975207] Already setup the GSI :16 Jul 16 12:54:41 placka kernel: [ 6.975238] ath9k 0000:03:00.0: setting latency timer to 64 Jul 16 12:54:41 placka kernel: [ 7.024638] ath: EEPROM regdomain: 0x60 Jul 16 12:54:41 placka kernel: [ 7.024643] ath: EEPROM indicates we should expect a direct regpair map Jul 16 12:54:41 placka kernel: [ 7.024650] ath: Country alpha2 being used: 00 Jul 16 12:54:41 placka kernel: [ 7.024653] ath: Regpair used: 0x60 Jul 16 12:54:41 placka kernel: [ 7.067934] ieee80211 phy0: Selected rate control algorithm 'minstrel_ht' Jul 16 12:54:41 placka kerne...