search for: registerwithsubreg

On Jan 9, 2012, at 10:00 AM, Jakob Stoklund Olesen wrote: > > On Jan 8, 2012, at 11:18 PM, Demikhovsky, Elena wrote: > >> I'll explain what we see in the code. >> 1. The caller saves XMM registers across the call if needed (according to DEFS definition). >> YMMs are not in the set, so caller does not take care. > > This is not how the register allocator

...fRegNum<[30, -2, -2]>; def XMM14b: Register<"xmm14b">, DwarfRegNum<[31, -2, -2]>; def XMM15b: Register<"xmm15b">, DwarfRegNum<[32, -2, -2]>; // YMM Registers, used by AVX instructions let SubRegIndices = [sub_xmm, sub_xmmb] in { def YMM0: RegisterWithSubRegs<"ymm0", [XMM0, XMM0b]>, DwarfRegNum<[17, 21, 21]>; def YMM1: RegisterWithSubRegs<"ymm1", [XMM1, XMM1b]>, DwarfRegNum<[18, 22, 22]>; def YMM2: RegisterWithSubRegs<"ymm2", [XMM2, XMM2b]>, DwarfRegNum<[19, 23, 23]>; def YMM3: Reg...

...v2, 1 > > > Evan > This is how my register classes look like: def FSR0L : Register<"FSR0L">; def FSR0H : Register<"FSR0H">; def FSR1L : Register<"FSR1L">; def FSR1H : Register<"FSR1H">; def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L, FSR1H]>; def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {...

Hello, Artur > I've compared again everything to systemz. The problem was I've defined > paired class as a subclass of Register class instead of RegisterWithSubRegs > class. After change the code is OK. Ok, nice > Yes, I have those. > If you don't mind I'll ask few compilers/LLVM newbie questions. > I'd appreciate if someone could enlighten me on pseudo instructions. > These work fine if I want to print assembly. What if I want to...

...r0:r1 > > Could anyone tell me what am I doing wrong? > Have you defined aliases properly? Look how this is handled inside > s390 backend (systemz). I've compared again everything to systemz. The problem was I've defined paired class as a subclass of Register class instead of RegisterWithSubRegs class. After change the code is OK. > Note that in general you'll need to write "paired" reg-reg mov pseudo > instructions. > Yes, I have those. If you don't mind I'll ask few compilers/LLVM newbie questions. I'd appreciate if someone could enlighten me on p...

...gt;> > > This is how my register classes look like: > > def FSR0L : Register<"FSR0L">; > def FSR0H : Register<"FSR0H">; > def FSR1L : Register<"FSR1L">; > def FSR1H : Register<"FSR1H">; > > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; > > def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L, > FSR1H]>; > > def FSR16RC : RegisterClass<"PIC16", [i16], 8...

...gister classes look like: > > > > def FSR0L : Register<"FSR0L">; > > def FSR0H : Register<"FSR0H">; > > def FSR1L : Register<"FSR1L">; > > def FSR1H : Register<"FSR1H">; > > > > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; > > > > def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L, > > FSR1H]>; > > > > def FSR16RC : RegisterClass&...

...ook like: >>> >>> def FSR0L : Register<"FSR0L">; >>> def FSR0H : Register<"FSR0H">; >>> def FSR1L : Register<"FSR1L">; >>> def FSR1H : Register<"FSR1H">; >>> >>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; >>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; >>> >>> def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L, >>> FSR1H]>; >>> >>> def FSR16RC :...

On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > What’s the value produced by an INSERT_SUBREG node? Is it a chain? No, insert_subreg returns a value: v1 = insert_subreg v2, v3, idx v1 and v2 will have the same type, e.g. i16, and v3 must have a sub- register type, e.g. i8. > Can I use to set a superreg of i16 type with two i8 values, and use > the supperreg as

What's the value produced by an INSERT_SUBREG node? Is it a chain? Can I use to set a superreg of i16 type with two i8 values, and use the supperreg as an operand somewhere else? - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081002/f07bc88c/attachment.html>

...t;>> def FSR0L : Register<"FSR0L">; > >>> def FSR0H : Register<"FSR0H">; > >>> def FSR1L : Register<"FSR1L">; > >>> def FSR1H : Register<"FSR1H">; > >>> > >>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > >>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; > >>> > >>> def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L, > >>> FSR1H]>; > >>> &g...

...the hi and lo > registers for those 64bit registers. > > So something like this: > def lo_comp : SubRegIndex; > def hi_comp : SubRegIndex; > def R1 : Register<1>; > def R2 : Register<2>; > def R3 : Register<1>; > def R4 : Register<2>; > def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; > > This says that D1 is a register with two components, lo and hi. When you > allocate D1, you also use R1/R2. > def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> > ... > def GPR64 : RegisterClass&lt...

...FSR0L : Register<"FSR0L">; >>>>> def FSR0H : Register<"FSR0H">; >>>>> def FSR1L : Register<"FSR1L">; >>>>> def FSR1H : Register<"FSR1H">; >>>>> >>>>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; >>>>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; >>>>> >>>>> def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, >>>>> FSR0L, >>>>&g...

...t as sub registers what you want to represent as the hi and lo registers for those 64bit registers. So something like this: def lo_comp : SubRegIndex; def hi_comp : SubRegIndex; def R1 : Register<1>; def R2 : Register<2>; def R3 : Register<1>; def R4 : Register<2>; def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/R2. def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> ... def GPR64 : RegisterClass<..., [i64], [64], (add D1)&g...

On Mips 32 there is traditionally a 64 bit HI/LO register for the result of multiplying two 64 bit numbers. There are corresponding instructions to load the LO and HI parts into individual 32 registers. On Mips with the DSP ASE (an application specific extension), there are actual 4 such pairs of registers. Is there a way to have special purpose 64 bit registers without actually having to

...nside another regclass of size i16, marking the pairs as subregs of the 8bit regs this way: <stripped version of my code)> // 8 bit regs def R0 : Register<"r0">, DwarfRegNum<[0]>; def R1 : Register<"r1">, DwarfRegNum<[1]>; // reg pairs def R1R0 : RegisterWithSubRegs<"r0", [R0, R1]>, DwarfRegNum<[0]>; def GPR8 : RegisterClass<"TEST", [i8], 8, [R0, R1]>; def WDREGS : RegisterClass<"TEST", [i16], 16, [R1R0]> { let SubRegClassList = [GPR8, GPR8]; } This way i could work with register pairs easily, for e...

hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<"t0",[R0,R1]>; ... def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] In mytargetISelLowering.cpp: I define i1, i8 , i16 and i32 are legal. 1. I still have problem. I save my function return double  value in R0 and R1.  It is expanded into two i32. But...

...those 64bit registers. > > So something like this: > def lo_comp : SubRegIndex; > def hi_comp : SubRegIndex; > def R1 : Register<1>; > def R2 : Register<2>; > def R3 : Register<1>; > def R4 : Register<2>; > def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; > > This says that D1 is a register with two components, lo and hi. > When you allocate D1, you also use R1/R2. > def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", > 1, 4))> ... > def GPR6...

...t as sub registers what you want to represent as the hi and lo registers for those 64bit registers. So something like this: def lo_comp : SubRegIndex; def hi_comp : SubRegIndex; def R1 : Register<1>; def R2 : Register<2>; def R3 : Register<1>; def R4 : Register<2>; def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/R2. def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> ... def GPR64 : RegisterClass<..., [i64], [64], (add D1)&g...

...se 64bit registers. >> >> So something like this: >> def lo_comp : SubRegIndex; >> def hi_comp : SubRegIndex; >> def R1 : Register<1>; >> def R2 : Register<2>; >> def R3 : Register<1>; >> def R4 : Register<2>; >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>; >> >> This says that D1 is a register with two components, lo and hi. When you >> allocate D1, you also use R1/R2. >> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> >> ... >> def...