search for: registertypeforvt

...w logical operations are legal on i8? Thanks, Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum PS: I have tried to tweak the TransformToType table to specify the type promotion i8 -> i32, by doing the following just after the call to computeRegisterProperties: RegisterTypeForVT[MVT::i8] = TransformToType[MVT::i8] = MVT::i32; and then legalize the SETCC on i8 and specify that for example the results of loads should be in i32 regs: setOperationAction(ISD::SETCC, MVT::i8, Legal); [...] setOperationAction(ISD::LOAD, MVT::i8, Promote); [...]

...--------- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) commit c53e2efbd52ac2a4690fe69c8ea4acad113956e0 Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Wed Dec 5 13:03:33 2012 +0100 Change TargetLowering::RegisterTypeForVT to store MVTs, instead of EVTs. include/llvm/Target/TargetLowering.h | 8 ++++---- lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 2 +- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 ++-- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 2 +- lib/CodeGen/SelectionD...

..., > Sebastian > -- > Qualcomm Innovation Center, Inc is a member of Code Aurora Forum > > PS: I have tried to tweak the TransformToType table to specify the > type promotion i8 -> i32, by doing the following just after the call > to computeRegisterProperties: > > RegisterTypeForVT[MVT::i8] = TransformToType[MVT::i8] = MVT::i32; > > and then legalize the SETCC on i8 and specify that for example the > results of loads should be in i32 regs: > > setOperationAction(ISD::SETCC, MVT::i8, Legal); > [...] > setOperationAction(ISD::LOAD, MVT::i8, P...

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > however, is that they are 8 bits.  The reason for this is

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as