search for: registertuples

...the register tuples was borrowed from SIRegisterInfo.td in AMD GPU. But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type. So I have to start defining the registers from 'byte' type, and then build up other type registers through RegisterTuples. I thought RegisterTuple is kind of expressing register alias in RegisterInfo.td file. I am not sure whether I understand it correctly. My first trial was like below(to make things simple, I remove some WORD/QWORD register class): let Namespace = "IntelGPU" in { foreach Index = 0-15 in {...

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r#

Hi, I have a problem during my development of a backend. There are some target instructions with multiple outputs, for example an instructionX with 2 inputs and 2 outputs: def1, def2 = InstructionX op1, op2 The defs above must be allocated in consecutive target physical registers. Is it possible to describe the constraints with tablegen and let the register allocator get all the things

Hi all, Can someone please explain me how to use REG_SEQUENCE in tablegen? The arch i'm writing backend for has 32-bit regs, and it has a couple of 64-bit load/store instructions which use two neighboring regs at once, which i'm trying to employ using virtual regs with subs. For example, it I want to move one 64-bit virtual reg to another, I'm trying to use the following pattern:

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing

On Jun 21, 2011, at 10:20 AM, Jakob Stoklund Olesen wrote: > > On Jun 21, 2011, at 9:23 AM, Jim Grosbach wrote: > >> >> On Jun 21, 2011, at 8:51 AM, Jakob Stoklund Olesen wrote: >> >>> In the past, I've seen some pushback on the list against adding more register classes. You can see it in the code as well,

...We also need to address the problem with register aliases. Currently, we don't model register sequence constraints properly for ARM NEON registers. I want to expand the current model of using QQ and QQQQ registers, but it would create more register aliases by adding pseudo super-registers. The RegisterTuples I added to TableGen recently are meant for this, but I don't want to add them to the ARM target until we have compile time under control. > And the new regalloc is not yet designed to scale with the number of register aliases. (But that could be fixed under some limited definition of aliasi...

On Jun 21, 2011, at 9:23 AM, Jim Grosbach wrote: > > On Jun 21, 2011, at 8:51 AM, Jakob Stoklund Olesen wrote: > >> In the past, I've seen some pushback on the list against adding more register classes. You can see it in the code as well, TargetLowering::getRegClassForInlineAsmConstraint() returns a vector of registers instead of a real register class. >> >> What