Displaying 3 results from an estimated 3 matches for "registertargetcode".
2010 May 17
0
[LLVMdev] ARM EABI Exceptions
Hello, Renato
> Anyone has any idea on the status of exception handling in clang/LLVM?
> DwarfException cannot be easily overwritten, and adding target specific
> code to it seems wrong...
Neither llvm-gcc nor clang support exceptions on ARM (except, maybe,
sjlj excheptions on arm/darwin). I have some patched uncommitted for
EH on ARM but they are too far from being complete.
--
With
2010 May 17
3
[LLVMdev] ARM EABI Exceptions
Hi,
I was comparing the way LLVM generates the exception table and it looks
a bit different from what GCC (arm-none-eabi-g++) generates.
Maybe that's because clang is not generating ARM IR when I do:
$ clang -c -emit-llvm -march=arm -mcpu=cortex-a8 -mtriple=arm-none-eabi
exception.cpp -o exception.clang.bc
clang: warning: argument unused during compilation: '-mcpu=cortex-a8'
clang:
2010 May 18
6
[LLVMdev] ARM EABI Exceptions
...backs to target-specific code (nor registration of such mechanism). To change that in line with AsmWriter would be a major change and passing a ARMException reference through AsmWriter would pass the object through many places that are not concerned with it.
A simple registration mechanism (DE->registerTargetCode-thingy) would be the least change and more direct approach, but it's damn ugly. ;)
Apart from that, the format of the table and the calls to intrinsic functions are quite close.
About Sj/Lj exceptions, that's not ARM EHABI compliant. EABI GCC won't compile that, I guess. Not to mentio...