search for: registerscavenging

There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that appears to get tripped on targets that don't have subregisters defined: bool SubUsed = false; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) if (isUsed(SubReg)) { SubUsed = true;...

No, I wasn't having a management lobotomy moment. If the target's registers have no subregisters, SubUsed is false and the assert gets tripped. Ok, back to the original question: What was the original intent in this code (lines 186-193 in lib/CodeGen/RegisterScavenging.cpp)? -scooter On Thu, Feb 25, 2010 at 7:00 PM, Scott Michel <scooter.phd at gmail.com> wrote: > Ugh. Management lobotomy kicked in. Need to RTFC better. > > > On Thu, Feb 25, 2010 at 6:18 PM, Scott Michel <scooter.phd at gmail.com>wrote: > >> There's an ass...

Ugh. Management lobotomy kicked in. Need to RTFC better. On Thu, Feb 25, 2010 at 6:18 PM, Scott Michel <scooter.phd at gmail.com> wrote: > There's an assert at line 192, lib/CodeGen/RegisterScavenging.cpp that > appears to get tripped on targets that don't have subregisters defined: > > bool SubUsed = false; > for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); > unsigned SubReg = *SubRegs; ++SubRegs) > if (isUsed(SubReg)) { &...

...ichel skrev: > No, I wasn't having a management lobotomy moment. If the target's registers have > no subregisters, SubUsed is false and the assert gets tripped. > > Ok, back to the original question: What was the original intent in this code > (lines 186-193 in lib/CodeGen/RegisterScavenging.cpp)? You beat me to it :). A simple bypass (patch attached) does at least not break 'make check' with x86 and SPU backends. (And fixes the problem with call.ll-test breaking when the SPU bigframes patch is applied) kalle -------------- next part -------------- A non-text attachment was...

...register and do not need the full feature set of the RegisterScavenger. - Matthias > On Jan 19, 2017, at 5:50 AM, Nemanja Ivanovic via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I believe what you're after is the register scavenger. > It's in: include/llvm/CodeGen/RegisterScavenging.h > Implementation: lib/CodeGen/RegisterScavenging.cpp > > On Thu, Jan 19, 2017 at 1:36 PM, Hong Hu via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > Hi All, > > Given a machine instruction, is it possible to tell which register(s...

...he RegisterScavenger. >> >> - Matthias >> >> On Jan 19, 2017, at 5:50 AM, Nemanja Ivanovic via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >> I believe what you're after is the register scavenger. >> It's in: include/llvm/CodeGen/RegisterScavenging.h >> Implementation: lib/CodeGen/RegisterScavenging.cpp >> >> On Thu, Jan 19, 2017 at 1:36 PM, Hong Hu via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> Hi All, >>> >>> Given a machine instruction, is it possible to tell which...

Hi All, Given a machine instruction, is it possible to tell which register(s) is still not in use? For example, given one instruction A, if the one follows it (say B) defines register rax, then I can tell rax should spare at instruction A. The purpose is to use the spare register to replace registers used by A, for instrumentation purpose. Regards, Hu Hong -------------- next part

On Feb 28, 2010, at 11:49 PM, <Kalle.Raiskila at nokia.com> <Kalle.Raiskila at nokia.com> wrote: > Jakob Stoklund Olesen skrev: >> On Feb 26, 2010, at 10:09 AM, Scott Michel wrote: >>> This patch now causes new problems in the CellSPU >>> backend (more stqd's and lqd's), so I have to investigate those >>> before committing the patch. >

...n't having a management lobotomy moment. If the target's > registers have > > no subregisters, SubUsed is false and the assert gets tripped. > > > > Ok, back to the original question: What was the original intent in this > code > > (lines 186-193 in lib/CodeGen/RegisterScavenging.cpp)? > > You beat me to it :). A simple bypass (patch attached) does at least not > break 'make check' with x86 and SPU backends. (And fixes the problem > with call.ll-test breaking when the SPU bigframes patch is applied) > > kalle > -------------- next part ---------...

...9 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same thing. > R4 is marked <kill> at MBB0. If I scan R4's liverange by [MBB0->MBB1->MBB2]. I will find R4 first is killed, then is used. It can not unlogisch. Attually R4 just is <Used>. It will cause my optimization pass c...

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's

...o llc causes a huge number of failures in the llvm-test-suite. We get approximately a 60% pass rate. This occurs when we link llvm object files with llvm-link, then generate the code using llc. The failures are a mix of llc assertions and runtime segfaults. 2. The following assertion failure in RegisterScavenging.cpp (using llc2.6): llc-2.6: /home/build/3rdparty/llvm-2.6-src/lib/CodeGen/RegisterScavenging.cpp:226: void llvm::RegScavenger::forward(): Assertion `(KillRegs.test(Reg) || isUnused(Reg) || isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && "Re-defining a live register!"' fa...

...m Cc: via llvm-dev Subject: Re: [llvm-dev] New to LLVM. Need help getting available register m m via llvm-dev <llvm-dev at lists.llvm.org> writes: > I'm new to LLVM. I'd like to know if there is a method I can call > whenever I need any available CPU register. Take a look at RegisterScavenging. Of course, this only works after register allocation. Before register allocation you'd just create a new virtual register. -David -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attach...

I ran into another issue with register scavenger. In my case, I don't need a place on the stack for an emergency spill slot. I have these free mips32 registers, that are not in general very useful for other things, for the emergency spill slot. I can move to and from mips16 (subset of mips32) registers and mips32 registers. I also have a situation where I need two free registers so then

...d kill flags on register operands. Simply put, a register is live from a <def> operand to a <use,kill> operand. It must not be used when it isn't live. The rules get tricky when sub-registers are involved. Your best bet for documentation is to read MachineVerifier.cpp and perhaps RegisterScavenging.cpp. If you are rearranging instructions, you must make sure that any kill flags are moved to the last instruction using a register. /jakob

Hi! I started writing a LLVM backend for a custom architecture. I have some register and instruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class

Hi, I would like to know what register scavenging is, but reading RegisterScavenging.h [1] and googling don't help too much. Could someone explain it a little bit (what it is and when we need it), or point me to some nice link, I will be very appreciated. :-) [1] http://llvm.org/docs/doxygen/html/RegisterScavenging_8h_source.html Regards, chenwj -- Wei-Ren Chen (陳韋任) Homepag...

Hi, I'm new to LLVM. I'd like to know if there is a method I can call whenever I need any available CPU register. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181222/e916b214/attachment.html>

On Sep 3, 2013, at 17:21 , Manuel Jacob <me at manueljacob.de> wrote: > The problem is to safe registers that contain gc pointers to the stack > before a call and reload them after the call. Is there an Analysis Pass > that computes information about which registers are live during a > specific instruction? I looked at LiveIntervals and LiveVariables, but > they seem to be for

You mean when I "explicity" use it by calling methods of register scavenger? Right now I'm just allocating virtual registers that will be resolved by the use of register scavenger and I'm also providing an override of the virtual method saveScavengerRegister. In Mips16, I have an extra mips 32 register (not usually very useful since it can only be used in a move instruction)