search for: registerpressur

> On Aug 30, 2017, at 1:43 PM, Matthias Braun <matze at braunis.de> wrote: > > That means you cannot use the code from RegisterPressure.{cpp|h} to compute this. The other liveness analysis we have in llvm codegen is LiveIntervals (LiveItnervalAnalysis) which gives you a list of liveness segments of a given vreg (the same representation is used in most linear scan allocators even though LLVM is not using a linear scan approach any...

...isUndef flags however are required to be correct. > > Undef yes, but what relies on isDead being accurate (before live interval computation)? I only remember Andy/Quentin making those conservative correctness claims about the kill flags but not the dead/undef flags. I am also pretty sure the RegisterPressure.cpp / -verify-misched fail on missing dead flags (although -verify-misched fails in several instances anyway at the moment...) On the other hand I just checked the MachineVerifier which indeed only checks for sonervatively correct dead flags as you say and I can't think of other places being...

...however are required to be correct. >> >> Undef yes, but what relies on isDead being accurate (before live interval computation)? > I only remember Andy/Quentin making those conservative correctness claims about the kill flags but not the dead/undef flags. I am also pretty sure the RegisterPressure.cpp / -verify-misched fail on missing dead flags (although -verify-misched fails in several instances anyway at the moment...) I re-checked the RegisterPressure.cpp code as well and it does not rely on dead-flags either (if there is no dead flag it queries the liveinterval for it). So it seems you...

Hi everyone, I'm looking through codes related to registered pressure tracking, mainly the source files 'RegisterPressure.h/cpp', 'MachineRegisterInfo.h/cpp', 'TargetRegisterInfo.h/cpp'. There is a concept I can hardly understand, the 'register pressure set'. Class 'TargetRegisterInfo' defines two virtual methods 'getRegClassPressureSets' and 'getRegUnitPressureSets...

Thanks for the suggestion. I tried your fix. It worked for my particular case, but then I got a following error: clang-3.5: /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: void decreaseSetPressure(std::vector<unsigned int>&, llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed. Do you mind helping me out? A stack dump is provided below: clang-3.5: /home/rail/projects/e...

Hi, I was looking into how SelectionDAG scheduling is done in LLVM for different backends, and I noticed that for the X86 backend, even though it sets scheduling preferences of ILP or RegisterPressure depending on architecture, in the end, it ends up using source scheduling. I realized this is because it overrides enableMachineScheduler to return true. Is there any specific reasons why it was done this way, and also, what happens to be class mainly responsible for the X86 scheduling then? Than...

...7/2016 3:44 PM, Rail Shafigulin wrote: > >> Thanks for the suggestion. >> >> I tried your fix. It worked for my particular case, but then I got a >> following error: >> >> clang-3.5: >> >> /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: >> void decreaseSetPressure(std::vector<unsigned int>&, >> llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= Weight && >> "register pressure underflow"' failed. >> >> Do you mind helping me out? A stack dump is provi...

...unga via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > I was looking into how SelectionDAG scheduling is done in LLVM for > different backends, and I noticed that for the X86 backend, even though it > sets scheduling preferences of ILP or RegisterPressure depending on > architecture, in the end, it ends up using source scheduling. I realized > this is because it overrides enableMachineScheduler to return true. Is > there any specific reasons why it was done this way, and also, what happens > to be class mainly responsible for the X86 sc...

On 7/28/2016 4:10 PM, Matthias Braun wrote: > > I re-checked the RegisterPressure.cpp code as well and it does not rely on dead-flags either (if there is no dead flag it queries the liveinterval for it). So it seems you are right with the statement of dead flags being optional. Cool. Thanks for double-checking. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of...

...for you, so you do not need to worry about them. Cheers, -Quentin > On May 23, 2016, at 12:57 AM, Xing Su via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi everyone, > > I'm looking through codes related to registered pressure tracking, mainly the source files 'RegisterPressure.h/cpp', 'MachineRegisterInfo.h/cpp', 'TargetRegisterInfo.h/cpp'. > > There is a concept I can hardly understand, the 'register pressure set'. Class 'TargetRegisterInfo' defines two virtual methods 'getRegClassPressureSets' and 'getRegUnitPres...

...gt; > Thanks for the suggestion. > > I tried your fix. It worked for my particular case, but then > I got a > following error: > > clang-3.5: > /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: > void decreaseSetPressure(std::vector<unsigned int>&, > llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= > Weight && > "register pressure underflow"' failed. > > Do y...

...a pointer to the code: https://gitlab.com/CSUS_LLVM/LLVM_DRAGONEGG/blob/master/Generic/llvmTip/llvm-master/lib/CodeGen/MachineScheduler.cpp#L921 And here is a pointer to the function initLiveThru() https://gitlab.com/CSUS_LLVM/LLVM_DRAGONEGG/blob/master/Generic/llvmTip/llvm-master/lib/CodeGen/RegisterPressure.cpp#L318 Thanks Ghassan Shobaki Assistant Professor of Computer Science California State University, Sacramento ________________________________ From: Jonas Paulsson <paulsson at linux.vnet.ibm.com> Sent: Monday, September 11, 2017 3:15:29 AM To: Andrew Trick; Matthias Braun Cc: Shoba...

Hello, In a previous email, Matthias mentioned that register pressure estimates in the machine scheduler are not absolute; they only account for the registers that are used in the block.I assume that he meant that registers that are live-through (both live-in and live-out) are not accounted for in register pressure calculations. If a register is either live-in or live-out but not both, it must be

I was handed a makefile which is used to compile a library and was told to figure out why the compilation is failing. There is a lot of output and at this point I'm not sure what is important and what is not. I'm trying to solve this problem in small steps, so if asked I can certainly provide more information. The first error that I see during compilation is

...ch as possible, the standard scheduling algorithm will be built from standalone utilities and data structures. The customizations that you describe would all be handled by providing a new MachineSchedStrategy. Start by composing your scheduler from the pieces that are available, e.g. HazardChecker, RegisterPressure... (There's not much value providing a scheduling queue abstraction on top of vector or priority_queue). From that point, we can improve the design. Here's what you can expect in the MachineScheduler: 1. Precise register pressure tracking with back off. I'm in the process of checking...

...trunk to write their own target-specific scheduler based on the pieces that are already available. Hexagon developers are doing this now. The LLVM toolkit for scheduling is all there--not perfect, but ready for developers. - Pluggable MachineScheduler pass - Scheduling DAG - LiveInterval Update - RegisterPressure tracking - InstructionItinerary and HazardChecker (to be extended) If you would simply like improved X86 scheduling without rolling your own, then providing feedback and test cases is useful so we can incorporate improvements into the standard scheduler while it's being developed. >> F...

...c scheduler > based on the pieces that are already available. Hexagon developers > are doing this now. The LLVM toolkit for scheduling is all there--not > perfect, but ready for developers. > > - Pluggable MachineScheduler pass > - Scheduling DAG > - LiveInterval Update > - RegisterPressure tracking > - InstructionItinerary and HazardChecker (to be extended) > > If you would simply like improved X86 scheduling without rolling your > own, then providing feedback and test cases is useful so we can > incorporate improvements into the standard scheduler while it's bei...

The isKill must be correct if present, but a vreg may still be killed even if the operand has no Kill flag. The isDead and isUndef flags however are required to be correct. We need further details to say anything about your problem, a LiveIntervals::dump() dump for example would be helpful to assess whether the liveness data is correct in your case. - Matthias > On Jul 28, 2016, at 1:42 PM,

On 7/28/2016 3:49 PM, Matthias Braun wrote: > > The isDead and isUndef flags however are required to be correct. Undef yes, but what relies on isDead being accurate (before live interval computation)? -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

...gister units compared to 160 registers, making it possible for the register allocator to track interference more compactly. Register units also enable accurate register pressure tracking in spite of overlapping register classes and aliasing registers. This is what Andy has been implementing in RegisterPressure.h. Register classes are mapped to corresponding sets of register units, and by counting units instead of registers, problems with aliasing registers go away. /jakob