Displaying 6 results from an estimated 6 matches for "registergroup".
2005 May 06
3
[LLVMdev] avoid live range overlap of "vector" registers
...ot;r0.z">;
def r0_w: FooReg<"r0.w">;
def r1_x: FooReg<"r1.x">;
def r1_y: FooReg<"r1.y">;
def r1_z: FooReg<"r1.z">;
def r1_w: FooReg<"r1.w">;
...
and there are 32 vector registers!
i've read Target.rd:
// RegisterGroup - This can be used to define instances of Register which
// need to specify aliases.
// List "aliases" specifies which registers are aliased to this one. This
// allows the code generator to be careful not to put two values with
// overlapping live ranges into registers which alias.
cla...
2004 Nov 16
2
[LLVMdev] Target.td:Register changes
...t the fresh CVS state I see:
class Register<string n> : RegisterBase<n> {
list<RegisterBase> Aliases = [];
}
while previously the Register class did not require any parameters. The change
log is just:
* Target.td: Revamp the Register class, and allow the use of the
RegisterGroup class to specify aliases directly in register
definitions.
and I could not find any discussions in the archives.
Why the change was necessary? Writing:
def gr0 : Register<"gr0">;
def gr1 : Register<"gr1">;
def gr2 : Register<"gr2">;...
2005 May 10
0
[LLVMdev] avoid live range overlap of "vector" registers
...gt;;
> def r1_x: FooReg<"r1.x">;
> def r1_y: FooReg<"r1.y">;
> def r1_z: FooReg<"r1.z">;
> def r1_w: FooReg<"r1.w">;
> ...
>
> and there are 32 vector registers!
>
>
> i've read Target.rd:
>
> // RegisterGroup - This can be used to define instances of Register which
> // need to specify aliases.
> // List "aliases" specifies which registers are aliased to this one. This
> // allows the code generator to be careful not to put two values with
> // overlapping live ranges into registe...
2004 Sep 14
0
[LLVMdev] TableGen target description file change
...specified as an argument for the register. If you had this:
def FP0 : Register;
before, change it to:
def FP0 : Register<"FP0">;
2. The RegisterAliases tablegen class is now gone. Instead, alias lists
are encoded directly into the Register class, through the use of the
RegisterGroup class. In the X86 backend, we used to have:
def AL : Register;
...
def : RegisterAliases<AL, [AX, EAX]>;
Now you can just define:
def AL : RegisterGroup<"AL", [AX, EAX]>;
Thanks to Jason for supplying this patch!
-Chris
--
http://llvm.org/
http://nondot.org/sabre/
2004 Nov 16
0
[LLVMdev] Target.td:Register changes
.... X86 has "ST(0)".
3. Having support for both "has an explicit name" and "does not have an
explicit name" means we need to have duplicate tblgen classes, e.g.
NamedRegister vs Register. I think the reason for making this change
was because we were introducing RegisterGroup and didn't want to have
to introduce NamedRegisterGroup for consistency.
-Chris
--
http://llvm.org/
http://nondot.org/sabre/
2005 Sep 17
1
[LLVMdev] Subword register allocation
...sting LLVM live interval analysis and register allocators. I wish
them could be re-used without modification, and perhaps using some
tricks in the TableGen .td file.
I don't know how to do it, but it may be like what is done in
X86RegisterInfo.td. AL and AH are defined to be the alias of AX by
RegisterGroup. But this method doesn't seem work. I'm not sure, and I
need your comments before implementing this similar techniques because
I have a tight schedule.
REFERENCES
[1] S. Tallam and R. Gupta, "Bitwidth aware global register
allocation", Annual Symposium on Principles of Progra...