Displaying 10 results from an estimated 10 matches for "registerbankinfo".
2016 Jul 28
1
[GlobalISel] Can we drop RegisterBankInfo::getInstrAlternativeMappings() ?
Hi,
I've spent some time playing around with GlobalISel on the AMDGPU target, and I
was wondering if there is any reason to have
RegisterBankInfo::getInstrAlternativeMappings() and
RegisterBankInfo::getInstrMapping() as separate functions.
Could we instead replace these two functions with just one:
RegisterBankInfo::getInstrMappings() and then just treat the first mapping
in the list as the 'default' mapping to use for 'Fast'...
2018 Dec 20
2
RegBankSelect complex value mappings
Hi,
I’m looking at RegBankSelect’s partially implemented support for deciding to split a value between multiple registers and I’m wondering if it’s actually intended to solve the problem I’m trying to use it for. RegisterBankInfo.h has this example mapping table:
/// E.g.,
/// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
/// can expand the
/// <2 x 32-bit> add into 2 x 32-bit add.
///
/// Currently the TableGen-like file would look like:
/// \code
/// PartialMapping[] = {
/// /*32-b...
2017 Nov 14
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...in clang when using the __fp16 type. Here’s a reproducer:
__fp16 pass_f16(__fp16 p) {
return p;
}
$ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
clang-6.0: /work/llvm/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp:446: static void llvm::RegisterBankInfo::applyDefaultMapping(const llvm::RegisterBankInfo::OperandsMapper &): Assertion `OrigTy.getSizeInBits() == NewTy.getSizeInBits() && "Types with difference size cannot be handled by the default " "mapping"' failed.
#0...
2017 Nov 14
6
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...t;
>> __fp16 pass_f16(__fp16 p) {
>> return p;
>> }
>>
>> $ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
>> clang-6.0: /work/llvm/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp:446: static void llvm::RegisterBankInfo::applyDefaultMapping(const llvm::RegisterBankInfo::OperandsMapper &): Assertion `OrigTy.getSizeInBits() == NewTy.getSizeInBits() && "Types with difference size cannot be handled by the default " "mapping"' failed.
>&...
2017 Nov 17
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...Here’s a reproducer:
>
> __fp16 pass_f16(__fp16 p) {
> return p;
> }
>
> $ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
> clang-6.0: /work/llvm/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp:446: static void llvm::RegisterBankInfo::applyDefaultMapping(const llvm::RegisterBankInfo::OperandsMapper &): Assertion `OrigTy.getSizeInBits() == NewTy.getSizeInBits() && "Types with difference size cannot be handled by the default " "mapping"' failed.
>...
2019 Feb 26
3
Dealing with illegal operand mappings in RegBankSelect
> On Feb 21, 2019, at 12:18 AM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi Matt,
>
>> On Feb 20, 2019, at 4:49 PM, Arsenault, Matthew via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
>> Hi,
>>
>> Some operations on AMDGPU require operands which must be in a register
2019 Feb 27
2
Dealing with illegal operand mappings in RegBankSelect
...pple.com>> wrote:
>>>
>>> I don’t get what you mean by “applyMapping to deal with it”. Won’t applyMapping will insert copies to rewrite these, hence how is this different from what the repairing code does?
>>> Unless, maybe, you’re talking about the target specific RegisterBankInfo::applyMapping not RegBankSelect::applyMapping.
>>>
>>> If that’s the case what do you do in here that we could maybe generalize?
>>>
>> Sorry, I mean report them as legal so they are left as-is with no copy inserted. I can see the operand is illegal and do everyth...
2017 Nov 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...Here’s a reproducer:
>
> __fp16 pass_f16(__fp16 p) {
> return p;
> }
>
> $ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
> clang-6.0: /work/llvm/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp:446: static void llvm::RegisterBankInfo::applyDefaultMapping(const llvm::RegisterBankInfo::OperandsMapper &): Assertion `OrigTy.getSizeInBits() == NewTy.getSizeInBits() && "Types with difference size cannot be handled by the default " "mapping"' failed.
>...
2017 Nov 13
3
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
My only remaining concern is around ABI compatibility.
The following commit seems to indicate that in the previous round of evaluation, we didn’t find an existing ABI compatibility issue:
http://llvm.org/viewvc/llvm-project?view=revision&revision=311388.
I haven’t looked into the details of this issue - so maybe I’m worried over nothing?
I’m wondering if since then on your side
2020 Oct 09
2
GlobalISel round table follow up: register bank select
Hi Quentin,
Am 08.10.20 um 21:17 schrieb Quentin Colombet:
> Hi Dominik,
>
>> On Oct 8, 2020, at 5:03 AM, Dominik Montada
>> <dominik.montada at hightec-rt.com
>> <mailto:dominik.montada at hightec-rt.com>> wrote:
>>
>> Hi Quentin,
>>
>> thanks for picking up the conversation!
>>
>> > I think we should step back and