Displaying 2 results from an estimated 2 matches for "register_width".
2017 Jun 05
2
Backend implementation for an architecture with only majority operation instruction
...om> wrote:
> I'm having a hard time grasping what this ISA actually looks like.
>
> When you say that it has a single instruction that is a majority function,
> I assume something like this:
>
> MAJ rDst <- rSrc0, rSrc1, rSrc2
> Semantics:
> for (int i = 0; i < REGISTER_WIDTH; i++) {
> rDst[i] = maj(rSrc0[i], rSrc1[i], rSrc2[i]);
> }
> Where maj(a, b, c) = (a & b) | (a & c) | (b & c)
>
> But that doesn't make sense given your question.
>
> MAJ is a bitwise operation, so how do you implement arithmetic
> instructions with it? You...
2017 Jun 02
5
Backend implementation for an architecture with only majority operation instruction
Hello everyone,
I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what